PIC18F2420/2520/4420/4520
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
Power-on Reset,
Brown-out Reset
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Register
Applicable Devices
IPR2
PIR2
PIE2
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
11-1 1111
00-0 0000
00-0 0000
1111 1111
-111 1111
0000 0000
-000 0000
0000 0000
-000 0000
00-0 0000
0000 -111
1111 1111
1111 1111
1111 1111
11-1 1111
00-0 0000
00-0 0000
1111 1111
-111 1111
0000 0000
-000 0000
0000 0000
-000 0000
00-0 0000
0000 -111
1111 1111
1111 1111
1111 1111
uu-u uuuu
(1)
uu-u uuuu
uu-u uuuu
uuuu uuuu
-uuu uuuu
IPR1
PIR1
PIE1
(1)
uuuu uuuu
(1)
-uuu uuuu
uuuu uuuu
-uuu uuuu
uu-u uuuu
uuuu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
OSCTUNE
TRISE
TRISD
TRISC
TRISB
(5)
(5)
(5)
(5)
TRISA
1111 1111
1111 1111
uuuu uuuu
LATE
LATD
LATC
LATB
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
(5)
(5)
(5)
(5)
LATA
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTE
PORTD
PORTC
PORTB
---- xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
(5)
(5)
(5)
(5)
PORTA
xx0x 0000
uu0u 0000
uuuu uuuu
Legend:
u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as
PORTA pins, they are disabled and read ‘0’.
6: The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit (CONFIG3H<1>). When
PBADEN = 1, PCFG<2:0> = 000; when PBADEN = 0, PCFG<2:0> = 111.
DS39631E-page 52
© 2008 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
