PIC18F2420/2520/4420/4520
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
(3)
TOSU
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2420
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
2520
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4420
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
4520
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 -1-1
11-0 0-00
N/A
---0 0000
0000 0000
0000 0000
uu-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 000u
1111 -1-1
11-0 0-00
N/A
---0 uuuu
(3)
TOSH
uuuu uuuu
(3)
TOSL
uuuu uuuu
(3)
STKPTR
PCLATU
PCLATH
PCL
uu-u uuuu
---u uuuu
uuuu uuuu
(2)
PC + 2
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
(1)
INTCON
INTCON2
INTCON3
INDF0
uuuu uuuu
(1)
uuuu -u-u
(1)
uu-u u-uu
N/A
N/A
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
xxxx xxxx
N/A
---- 0000
uuuu uuuu
uuuu uuuu
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Legend:
u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as
PORTA pins, they are disabled and read ‘0’.
6: The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit (CONFIG3H<1>). When
PBADEN = 1, PCFG<2:0> = 000; when PBADEN = 0, PCFG<2:0> = 111.
© 2008 Microchip Technology Inc.
DS39631E-page 49
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