PIC18F2420/2520/4420/4520
16.4.4
HALF-BRIDGE MODE
FIGURE 16-4:
HALF-BRIDGE PWM
OUTPUT
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output signal
is output on the P1A pin, while the complementary PWM
output signal is output on the P1B pin (Figure 16-4). This
mode can be used for half-bridge applications, as shown
in Figure 16-5, or for full-bridge applications where four
power switches are being modulated with two PWM
signals.
Period
Period
Duty Cycle
(2)
(2)
P1A
td
td
P1B
In Half-Bridge Output mode, the programmable dead-
band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits,
PDC<6:0>, sets the number of instruction cycles before
the output is driven active. If the value is greater than
the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 16.4.6
“Programmable Dead-Band Delay” for more details
of the dead-band delay operations.
(1)
(1)
(1)
td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
Since the P1A and P1B outputs are multiplexed with
the PORTC<2> and PORTD<5> data latches, the
TRISC<2> and TRISD<5> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 16-5:
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
V+
Standard Half-Bridge Circuit (“Push-Pull”)
PIC18F4X2X
P1A
FET
Driver
+
V
-
Load
FET
Driver
+
V
-
P1B
V-
Half-Bridge Output Driving a Full-Bridge Circuit
V+
PIC18F4X2X
FET
FET
Driver
Driver
P1A
Load
FET
FET
Driver
Driver
P1B
V-
DS39631E-page 152
© 2008 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
