欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F4520-I/PT 参数 Datasheet PDF下载

PIC18F4520-I/PT图片预览
型号: PIC18F4520-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP TECHNOLOGY ]
 浏览型号PIC18F4520-I/PT的Datasheet PDF文件第131页浏览型号PIC18F4520-I/PT的Datasheet PDF文件第132页浏览型号PIC18F4520-I/PT的Datasheet PDF文件第133页浏览型号PIC18F4520-I/PT的Datasheet PDF文件第134页浏览型号PIC18F4520-I/PT的Datasheet PDF文件第136页浏览型号PIC18F4520-I/PT的Datasheet PDF文件第137页浏览型号PIC18F4520-I/PT的Datasheet PDF文件第138页浏览型号PIC18F4520-I/PT的Datasheet PDF文件第139页  
PIC18F2420/2520/4420/4520
13.0
TIMER2 MODULE
13.1
Timer2 Operation
The Timer2 module timer incorporates the following
features:
• 8-Bit Timer and Period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4
and 1:16)
• Software programmable postscaler (1:1 through
1:16)
• Interrupt on TMR2 to PR2 match
• Optional use as the shift clock for the MSSP
module
The module is controlled through the T2CON register
and configures the prescaler and postscaler. Timer2
can be shut off by clearing control bit, TMR2ON
(T2CON<2>), to minimize power consumption.
A simplified block diagram of the module is shown in
In normal operation, TMR2 is incremented from 00h on
each clock (F
OSC
/4). A 4-bit counter/prescaler on the
clock input gives direct input, divide-by-4 and divide-by-
16 prescale options; these are selected by the prescaler
control bits, T2CKPS<1:0> (T2CON<1:0>). The value of
TMR2 is compared to that of the Period register, PR2, on
each clock cycle. When the two values match, the com-
parator generates a match signal as the timer output.
This signal also resets the value of TMR2 to 00h on the
next cycle and drives the output counter/postscaler (see
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, while the PR2 register initializes at FFh.
Both the prescaler and postscaler counters are cleared
on the following events:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 13-1:
U-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-3
T2CON: TIMER2 CONTROL REGISTER
R/W-0
T2OUTPS2
R/W-0
T2OUTPS1
R/W-0
T2OUTPS0
R/W-0
TMR2ON
R/W-0
T2CKPS1
R/W-0
T2CKPS0
bit 0
R/W-0
T2OUTPS3
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented:
Read as ‘0’
T2OUTPS<3:0>:
Timer2 Output Postscale Select bits
0000
= 1:1 Postscale
0001
= 1:2 Postscale
1111
= 1:16 Postscale
TMR2ON:
Timer2 On bit
1
= Timer2 is on
0
= Timer2 is off
T2CKPS<1:0>:
Timer2 Clock Prescale Select bits
00
= Prescaler is 1
01
= Prescaler is 4
1x
= Prescaler is 16
bit 2
bit 1-0
©
2008 Microchip Technology Inc.
DS39631E-page 133