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PIC18F4520-I/P 参数 Datasheet PDF下载

PIC18F4520-I/P图片预览
型号: PIC18F4520-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
EXAMPLE 6-3:  
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)  
PROGRAM_MEMORY  
BSF  
BCF  
BSF  
BCF  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
BSF  
EECON1, EEPGD  
EECON1, CFGS  
EECON1, WREN  
INTCON, GIE  
55h  
EECON2  
0AAh  
EECON2  
; point to Flash program memory  
; access Flash program memory  
; enable write to memory  
; disable interrupts  
Required  
Sequence  
; write 55h  
; write 0AAh  
EECON1, WR  
INTCON, GIE  
EECON1, WREN  
; start program (CPU stall)  
; re-enable interrupts  
; disable write to memory  
BSF  
BCF  
6.5.2  
WRITE VERIFY  
6.5.4  
PROTECTION AGAINST  
SPURIOUS WRITES  
Depending on the application, good programming  
practice may dictate that the value written to the  
memory should be verified against the original value.  
This should be used in applications where excessive  
writes can stress bits near the specification limit.  
To protect against spurious writes to Flash program  
memory, the write initiate sequence must also be  
followed. See Section 23.0 “Special Features of  
the CPU” for more detail.  
6.5.3  
UNEXPECTED TERMINATION OF  
WRITE OPERATION  
6.6  
Flash Program Operation During  
Code Protection  
If a write is terminated by an unplanned event, such as  
loss of power or an unexpected Reset, the memory  
location just programmed should be verified and repro-  
grammed if needed. If the write operation is interrupted  
by a MCLR Reset or a WDT Time-out Reset during  
normal operation, the user can check the WRERR bit  
and rewrite the location(s) as needed.  
See Section 23.5 “Program Verification and Code  
Protection” for details on code protection of Flash  
program memory.  
TABLE 6-2:  
Name  
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY  
Reset  
Valueson  
page  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
TBLPTRU  
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)  
49  
49  
49  
49  
49  
51  
51  
52  
52  
52  
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)  
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)  
TABLAT  
INTCON  
Program Memory Table Latch  
GIE/GIEH PEIE/GIEL TMR0IE INT0IE  
RBIE  
TMR0IF  
INT0IF  
RBIF  
EECON2 EEPROM Control Register 2 (not a physical register)  
EECON1  
IPR2  
EEPGD  
OSCFIP  
OSCFIF  
OSCFIE  
CFGS  
CMIP  
CMIF  
CMIE  
FREE  
EEIP  
EEIF  
EEIE  
WRERR  
BCLIP  
BCLIF  
BCLIE  
WREN  
HLVDIP  
HLVDIF  
HLVDIE  
WR  
RD  
TMR3IP  
TMR3IF  
TMR3IE  
CCP2IP  
CCP2IF  
CCP2IE  
PIR2  
PIE2  
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.  
© 2008 Microchip Technology Inc.  
DS39631E-page 81  
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