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PIC18F4520-I/P 参数 Datasheet PDF下载

PIC18F4520-I/P图片预览
型号: PIC18F4520-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
6.4.1  
FLASH PROGRAM MEMORY  
ERASE SEQUENCE  
6.4  
Erasing Flash Program Memory  
The minimum erase block is 32 words or 64 bytes. Only  
through the use of an external programmer, or through  
ICSP control, can larger blocks of program memory be  
bulk erased. Word erase in the Flash array is not  
supported.  
The sequence of events for erasing a block of internal  
program memory location is:  
1. Load Table Pointer register with address of row  
being erased.  
When initiating an erase sequence from the micro-  
controller itself, a block of 64 bytes of program memory  
is erased. The Most Significant 16 bits of the  
TBLPTR<21:6> point to the block being erased.  
TBLPTR<5:0> are ignored.  
2. Set the EECON1 register for the erase operation:  
• set EEPGD bit to point to program memory;  
• clear the CFGS bit to access program memory;  
• set WREN bit to enable writes;  
• set FREE bit to enable the erase.  
3. Disable interrupts.  
The EECON1 register commands the erase operation.  
The EEPGD bit must be set to point to the Flash pro-  
gram memory. The WREN bit must be set to enable  
write operations. The FREE bit is set to select an erase  
operation.  
4. Write 55h to EECON2.  
5. Write 0AAh to EECON2.  
6. Set the WR bit. This will begin the row erase  
cycle.  
For protection, the write initiate sequence for EECON2  
must be used.  
7. The CPU will stall for duration of the erase  
(about 2 ms using internal timer).  
A long write is necessary for erasing the internal Flash.  
Instruction execution is halted while in a long write  
cycle. The long write will be terminated by the internal  
programming timer.  
8. Re-enable interrupts.  
EXAMPLE 6-2:  
ERASING A FLASH PROGRAM MEMORY ROW  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
CODE_ADDR_UPPER  
TBLPTRU  
CODE_ADDR_HIGH  
TBLPTRH  
CODE_ADDR_LOW  
TBLPTRL  
; load TBLPTR with the base  
; address of the memory block  
ERASE_ROW  
BSF  
BCF  
BSF  
BSF  
EECON1, EEPGD  
EECON1, CFGS  
EECON1, WREN  
EECON1, FREE  
INTCON, GIE  
55h  
EECON2  
0AAh  
EECON2  
EECON1, WR  
INTCON, GIE  
; point to Flash program memory  
; access Flash program memory  
; enable write to memory  
; enable Row Erase operation  
; disable interrupts  
BCF  
Required  
Sequence  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
BSF  
; write 55h  
; write 0AAh  
; start erase (CPU stall)  
; re-enable interrupts  
BSF  
DS39631E-page 78  
© 2008 Microchip Technology Inc.  
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