PIC18F2420/2520/4420/4520
The long write is necessary for programming the inter-
6.5
Writing to Flash Program Memory
nal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
The minimum programming block is 16 words or
32 bytes. Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 32 holding registers used by the table writes for
programming.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction may need to be executed
32 times for each programming operation. All of the
table write operations will essentially be short writes
because only the holding registers are written. At the
end of updating the 32 holding registers, the EECON1
register must be written to in order to start the
programming operation with a long write.
Note:
The default value of the holding registers on
device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte. This means indi-
vidual bytes of program memory may be
modified, provided that the change does not
attempt to change any bit from a ‘0’ to a ‘1’.
When modifying individual bytes, it is not
necessary to load all 32 holding registers
before executing a write operation.
FIGURE 6-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
8
8
TBLPTR = xxxxx0
TBLPTR = xxxxx1
TBLPTR = xxxxx2
TBLPTR = xxxx3F
Holding Register
Holding Register
Holding Register
Holding Register
Program Memory
8. Disable interrupts.
6.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
9. Write 55h to EECON2.
10. Write 0AAh to EECON2.
The sequence of events for programming an internal
program memory location should be:
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
2 ms using internal timer).
1. Read 64 bytes into RAM.
2. Update data values in RAM as necessary.
13. Re-enable interrupts.
3. Load Table Pointer register with address being
erased.
14. Verify the memory (table read).
This procedure will require about 6 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.
4. Execute the row erase procedure.
5. Load Table Pointer register with address of first
byte being written.
6. Write the 32 bytes into the holding registers with
auto-increment.
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 32 bytes in
the holding register.
7. Set the EECON1 register for the write operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN to enable byte writes.
© 2008 Microchip Technology Inc.
DS39631E-page 79
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