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PIC18F4520-I/P 参数 Datasheet PDF下载

PIC18F4520-I/P图片预览
型号: PIC18F4520-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
The PLUSW register can be used to implement a form  
of Indexed Addressing in the data memory space. By  
manipulating the value in the W register, users can  
reach addresses that are fixed offsets from pointer  
addresses. In some applications, this can be used to  
implement some powerful program control structure,  
such as software stacks, inside of data memory.  
5.5.1  
INDEXED ADDRESSING WITH  
LITERAL OFFSET  
Enabling the PIC18 extended instruction set changes  
the behavior of Indirect Addressing using the FSR2  
register pair within Access RAM. Under the proper  
conditions, instructions that use the Access Bank – that  
is, most bit-oriented and byte-oriented instructions –  
can invoke a form of Indexed Addressing using an  
offset specified in the instruction. This special address-  
ing mode is known as Indexed Addressing with Literal  
Offset, or Indexed Literal Offset mode.  
5.4.3.3  
Operations by FSRs on FSRs  
Indirect Addressing operations that target other FSRs  
or virtual registers represent special cases. For  
example, using an FSR to point to one of the virtual  
registers will not result in successful operations. As a  
specific case, assume that FSR0H:FSR0L contains  
FE7h, the address of INDF1. Attempts to read the  
value of the INDF1 using INDF0 as an operand will  
return 00h. Attempts to write to INDF1 using INDF0 as  
the operand will result in a NOP.  
When using the extended instruction set, this  
addressing mode requires the following:  
• The use of the Access Bank is forced (‘a’ = 0) and  
• The file address argument is less than or equal to  
5Fh.  
Under these conditions, the file address of the instruc-  
tion is not interpreted as the lower byte of an address  
(used with the BSR in direct addressing), or as an 8-bit  
address in the Access Bank. Instead, the value is  
interpreted as an offset value to an Address Pointer,  
specified by FSR2. The offset and the contents of  
FSR2 are added to obtain the target address of the  
operation.  
On the other hand, using the virtual registers to write to  
an FSR pair may not occur as planned. In these cases,  
the value will be written to the FSR pair but without any  
incrementing or decrementing. Thus, writing to INDF2  
or POSTDEC2 will write the same value to the  
FSR2H:FSR2L.  
Since the FSRs are physical registers mapped in the  
SFR space, they can be manipulated through all direct  
operations. Users should proceed cautiously when  
working on these registers, particularly if their code  
uses indirect addressing.  
5.5.2  
INSTRUCTIONS AFFECTED BY  
INDEXED LITERAL OFFSET MODE  
Any of the core PIC18 instructions that can use Direct  
Addressing are potentially affected by the Indexed  
Literal Offset Addressing mode. This includes all  
byte-oriented and bit-oriented instructions, or almost  
one-half of the standard PIC18 instruction set.  
Instructions that only use Inherent or Literal Addressing  
modes are unaffected.  
Similarly, operations by Indirect Addressing are gener-  
ally permitted on all other SFRs. Users should exercise  
the appropriate caution that they do not inadvertently  
change settings that might affect the operation of the  
device.  
Additionally, byte-oriented and bit-oriented instructions  
are not affected if they do not use the Access Bank  
(Access RAM bit is ‘1’), or include a file address of 60h  
or above. Instructions meeting these criteria will  
continue to execute as before. A comparison of the dif-  
ferent possible addressing modes when the extended  
instruction set is enabled in shown in Figure 5-9.  
5.5  
Data Memory and the Extended  
Instruction Set  
Enabling the PIC18 extended instruction set (XINST  
Configuration bit = 1) significantly changes certain  
aspects of data memory and its addressing. Specifi-  
cally, the use of the Access Bank for many of the core  
PIC18 instructions is different; this is due to the  
introduction of a new addressing mode for the data  
memory space.  
Those who desire to use byte-oriented or bit-oriented  
instructions in the Indexed Literal Offset mode should  
note the changes to assembler syntax for this mode.  
This is described in more detail in Section 24.2.1  
“Extended Instruction Syntax”.  
What does not change is just as important. The size of  
the data memory space is unchanged, as well as its  
linear addressing. The SFR map remains the same.  
Core PIC18 instructions can still operate in both Direct  
and Indirect Addressing mode; inherent and literal  
instructions do not change at all. Indirect Addressing  
with FSR0 and FSR1 also remains unchanged.  
DS39631E-page 70  
© 2008 Microchip Technology Inc.  
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