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PIC18F4520-I/P 参数 Datasheet PDF下载

PIC18F4520-I/P图片预览
型号: PIC18F4520-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
5.4.3.1  
FSR Registers and the INDF  
Operand  
5.4.3.2  
FSR Registers and POSTINC,  
POSTDEC, PREINC and PLUSW  
At the core of Indirect Addressing are three sets of reg-  
isters: FSR0, FSR1 and FSR2. Each represents a pair  
of 8-bit registers, FSRnH and FSRnL. The four upper  
bits of the FSRnH register are not used so each FSR  
pair holds a 12-bit value. This represents a value that  
can address the entire range of the data memory in a  
linear fashion. The FSR register pairs, then, serve as  
pointers to data memory locations.  
In addition to the INDF operand, each FSR register pair  
also has four additional indirect operands. Like INDF,  
these are “virtual” registers that cannot be indirectly  
read or written to. Accessing these registers actually  
accesses the associated FSR register pair, but also  
performs a specific action on it stored value. They are:  
• POSTDEC: accesses the FSR value, then  
automatically decrements it by 1 afterwards  
Indirect Addressing is accomplished with a set of  
Indirect File Operands, INDF0 through INDF2. These  
can be thought of as “virtual” registers: they are  
mapped in the SFR space but are not physically imple-  
mented. Reading or writing to a particular INDF register  
actually accesses its corresponding FSR register pair.  
A read from INDF1, for example, reads the data at the  
address indicated by FSR1H:FSR1L. Instructions that  
use the INDF registers as operands actually use the  
contents of their corresponding FSR as a pointer to the  
instruction’s target. The INDF operand is just a  
convenient way of using the pointer.  
• POSTINC: accesses the FSR value, then  
automatically increments it by 1 afterwards  
• PREINC: increments the FSR value by 1, then  
uses it in the operation  
• PLUSW: adds the signed value of the W register  
(range of -127 to 128) to that of the FSR and uses  
the new value in the operation.  
In this context, accessing an INDF register uses the  
value in the FSR registers without changing them. Sim-  
ilarly, accessing a PLUSW register gives the FSR value  
offset by that in the W register; neither value is actually  
changed in the operation. Accessing the other virtual  
registers changes the value of the FSR registers.  
Because Indirect Addressing uses a full 12-bit address,  
data RAM banking is not necessary. Thus, the current  
contents of the BSR and the Access RAM bit have no  
effect on determining the target address.  
Operations on the FSRs with POSTDEC, POSTINC  
and PREINC affect the entire register pair; that is, roll-  
overs of the FSRnL register from FFh to 00h carry over  
to the FSRnH register. On the other hand, results of  
these operations do not change the value of any flags  
in the STATUS register (e.g., Z, N, OV, etc.).  
FIGURE 5-8:  
INDIRECT ADDRESSING  
000h  
Using an instruction with one of the  
Indirect Addressing registers as the  
operand....  
Bank 0  
Bank 1  
ADDWF, INDF1, 1  
100h  
200h  
300h  
Bank 2  
FSR1H:FSR1L  
...uses the 12-bit address stored in  
the FSR pair associated with that  
register....  
7
0
7
0
Bank 3  
through  
Bank 13  
x x x x 1 1 1 0  
1 1 0 0 1 1 0 0  
...to determine the data memory  
location to be used in that operation.  
E00h  
In this case, the FSR1 pair contains  
ECCh. This means the contents of  
location ECCh will be added to that  
of the W register and stored back in  
ECCh.  
Bank 14  
Bank 15  
F00h  
FFFh  
Data Memory  
© 2008 Microchip Technology Inc.  
DS39631E-page 69  
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