欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F4520-I/P 参数 Datasheet PDF下载

PIC18F4520-I/P图片预览
型号: PIC18F4520-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F4520-I/P的Datasheet PDF文件第168页浏览型号PIC18F4520-I/P的Datasheet PDF文件第169页浏览型号PIC18F4520-I/P的Datasheet PDF文件第170页浏览型号PIC18F4520-I/P的Datasheet PDF文件第171页浏览型号PIC18F4520-I/P的Datasheet PDF文件第173页浏览型号PIC18F4520-I/P的Datasheet PDF文件第174页浏览型号PIC18F4520-I/P的Datasheet PDF文件第175页浏览型号PIC18F4520-I/P的Datasheet PDF文件第176页  
PIC18F2420/2520/4420/4520  
2
17.4.1  
REGISTERS  
17.4 I C Mode  
The MSSP module has six registers for I2C operation.  
These are:  
The MSSP module in I2C mode fully implements all  
master and slave functions (including general call  
support) and provides interrupts on Start and Stop bits  
in hardware to determine a free bus (multi-master  
function). The MSSP module implements the standard  
mode specifications, as well as 7-Bit and 10-Bit  
Addressing modes.  
• MSSP Control Register 1 (SSPCON1)  
• MSSP Control Register 2 (SSPCON2)  
• MSSP Status Register (SSPSTAT)  
• Serial Receive/Transmit Buffer Register  
(SSPBUF)  
Two pins are used for data transfer:  
• MSSP Shift Register (SSPSR) – Not directly  
accessible  
• Serial clock (SCL) – RC3/SCK/SCL  
• Serial data (SDA) – RC4/SDI/SDA  
• MSSP Address Register (SSPADD)  
The user must configure these pins as inputs or outputs  
through the TRISC<4:3> bits.  
SSPCON1, SSPCON2 and SSPSTAT are the control  
and status registers in I2C mode operation. The  
SSPCON1 and SSPCON2 registers are readable and  
writable. The lower 6 bits of the SSPSTAT are read-only.  
The upper two bits of the SSPSTAT are read/write.  
FIGURE 17-7:  
MSSP BLOCK DIAGRAM  
(I2C MODE)  
SSPSR is the shift register used for shifting data in or  
out. SSPBUF is the buffer register to which data bytes  
are written to or read from.  
Internal  
Data Bus  
Read  
Write  
SSPADD register holds the slave device address when  
the MSSP is configured in I2C Slave mode. When the  
MSSP is configured in Master mode, the lower seven  
bits of SSPADD act as the Baud Rate Generator reload  
value.  
SSPBUF reg  
RC3/SCK/SCL  
Shift  
Clock  
In receive operations, SSPSR and SSPBUF together  
create a double-buffered receiver. When SSPSR  
receives a complete byte, it is transferred to SSPBUF  
and the SSPIF interrupt is set.  
SSPSR reg  
RC4/SDI/  
SDA  
MSb  
LSb  
Match Detect  
Addr Match  
During transmission, the SSPBUF is not double-  
buffered. A write to SSPBUF will write to both SSPBUF  
and SSPSR.  
SSPADD reg  
Start and  
Set, Reset  
S, P bits  
(SSPSTAT reg)  
Stop bit Detect  
DS39631E-page 170  
© 2008 Microchip Technology Inc.  
 复制成功!