PIC18F2420/2520/4420/4520
REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MODE)
R/W-0
GCEN
R/W-0
R/W-0
ACKDT(2)
R/W-0
ACKEN(1)
R/W-0
RCEN(1)
R/W-0
PEN(1)
R/W-0
RSEN(1)
R/W-0
SEN(1)
ACKSTAT
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
GCEN: General Call Enable bit (Slave mode only)
1= Enables interrupt when a general call address (0000h) is received in the SSPSR
0= General call address disabled.
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1= Acknowledge was not received from slave
0= Acknowledge was received from slave
ACKDT: Acknowledge Data bit (Master Receive mode only)(2)
1= Not Acknowledge
0= Acknowledge
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)(1)
1= Initiates Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically
cleared by hardware.
0= Acknowledge sequence Idle
bit 3
bit 2
bit 1
bit 0
RCEN: Receive Enable bit (Master mode only)(1)
1= Enables Receive mode for I2C
0= Receive Idle
PEN: Stop Condition Enable bit (Master mode only)(1)
1= Initiates Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0= Stop condition Idle
RSEN: Repeated Start Condition Enable bit (Master mode only)(1)
1= Initiates Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Repeated Start condition Idle
SEN: Start Condition Enable/Stretch Enable bit(1)
In Master mode:
1= Initiates Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Start condition Idle
In Slave mode:
1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0= Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, these bits may not be
set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
2: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
© 2008 Microchip Technology Inc.
DS39631E-page 173
MICROCHIP [ MICROCHIP ]
