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PIC18F4520-I/P 参数 Datasheet PDF下载

PIC18F4520-I/P图片预览
型号: PIC18F4520-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
The timing for the control signals in Write and Read  
modes is shown in Figure 10-3 and Figure 10-4,  
respectively.  
10.6 Parallel Slave Port  
Note:  
The Parallel Slave Port is only available on  
40/44-pin devices.  
FIGURE 10-2:  
PORTD AND PORTE  
BLOCK DIAGRAM  
(PARALLEL SLAVE PORT)  
In addition to its function as a general I/O port, PORTD  
can also operate as an 8-bit wide Parallel Slave Port  
(PSP) or microprocessor port. PSP operation is con-  
trolled by the 4 upper bits of the TRISE register  
(Register 10-1). Setting control bit, PSPMODE  
(TRISE<4>), enables PSP operation as long as the  
Enhanced CCP module is not operating in dual output  
or quad output PWM mode. In Slave mode, the port is  
asynchronously readable and writable by the external  
world.  
One bit of PORTD  
Data Bus  
D
Q
RDx pin  
WR LATD  
or  
WR PORTD  
CK  
Data Latch  
TTL  
The PSP can directly interface to an 8-bit micro-  
processor data bus. The external microprocessor can  
read or write the PORTD latch as an 8-bit latch. Setting  
the control bit, PSPMODE, enables the PORTE I/O  
pins to become control inputs for the microprocessor  
port. When set, port pin RE0 is the RD input, RE1 is the  
WR input and RE2 is the CS (Chip Select) input. For  
this functionality, the corresponding data direction bits  
of the TRISE register (TRISE<2:0>) must be config-  
ured as inputs (set). The A/D port configuration bits,  
PFCG<3:0> (ADCON1<3:0>), must also be set to a  
value in the range of ‘1010’ through ‘1111’.  
Q
D
RD PORTD  
RD LATD  
EN  
Set Interrupt Flag  
PSPIF (PIR1<7>)  
A write to the PSP occurs when both the CS and WR  
lines are first detected low and ends when either are  
detected high. The PSPIF and IBF flag bits are both set  
when the write ends.  
PORTE Pins  
Read  
RD  
CS  
WR  
TTL  
Chip Select  
TTL  
A read from the PSP occurs when both the CS and RD  
lines are first detected low. The data in PORTD is read  
out and the OBF bit is clear. If the user writes new data  
to PORTD to set OBF, the data is immediately read out;  
however, the OBF bit is not set.  
Write  
TTL  
Note:  
I/O pins have diode protection to VDD and VSS.  
When either the CS or RD lines are detected high, the  
PORTD pins return to the input state and the PSPIF bit  
is set. User applications should wait for PSPIF to be set  
before servicing the PSP; when this happens, the IBF  
and OBF bits can be polled and the appropriate action  
taken.  
DS39631E-page 120  
© 2008 Microchip Technology Inc.  
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