PIC18F2420/2520/4420/4520
TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
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Values
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Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD
LATD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
52
52
52
52
51
PORTD Data Latch Register (Read and Write to Data Latch)
PORTD Data Direction Register
TRISD
TRISE(1)
IBF
P1M1(1)
OBF
P1M0(1)
IBOV
PSPMODE
—
TRISE2
TRISE1
TRISE0
CCP1CON
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
Note 1: These registers and/or bits are unimplemented on 28-oin devices.
DS39631E-page 116
© 2008 Microchip Technology Inc.