PIC18F2420/2520/4420/4520
TABLE 10-9: PORTE I/O SUMMARY
TRIS
Setting
I/O
Pin
Function
I/O
Description
Type
RE0/RD/AN5
RE0
0
1
1
1
0
1
1
1
0
1
1
1
—
O
I
DIG
ST
LATE<0> data output; not affected by analog input.
PORTE<0> data input; disabled when analog input enabled.
PSP read enable input (PSP enabled).
RD
I
TTL
ANA
DIG
ST
AN5
RE1
I
A/D input channel 5; default input configuration on POR.
LATE<1> data output; not affected by analog input.
PORTE<1> data input; disabled when analog input enabled.
PSP write enable input (PSP enabled).
RE1/WR/AN6
RE2/CS/AN7
MCLR/VPP/RE3
O
I
WR
AN6
RE2
I
TTL
ANA
DIG
ST
I
A/D input channel 6; default input configuration on POR.
LATE<2> data output; not affected by analog input.
PORTE<2> data input; disabled when analog input enabled.
PSP write enable input (PSP enabled).
O
I
CS
AN7
I
TTL
ANA
ST
I
A/D input channel 7; default input configuration on POR.
(1)
MCLR
I
External Master Clear input; enabled when MCLRE Configuration bit is
set.
VPP
—
I
I
ANA
ST
High-voltage detection; used for ICSP™ mode entry detection. Always
available regardless of pin mode.
(2)
RE3
—
PORTE<3> data input; enabled when MCLRE Configuration bit is
clear.
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: RE3 is available on both 28-pin and 40/44-pin devices. All other PORTE pins are only implemented on 40/44-pin
devices.
2: RE3 does not have a corresponding TRIS bit to control data direction.
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
PORTE
LATE(2)
TRISE
—
—
—
—
—
—
—
—
RE3(1,2)
—
RE2
RE1
RE0
52
52
52
51
LATE Data Latch Register
IBF
—
OBF
—
IBOV
VCFG1
PSPMODE
VCFG0
—
TRISE2
PCFG2
TRISE1
PCFG1
TRISE0
PCFG0
ADCON1
PCFG3
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
© 2008 Microchip Technology Inc.
DS39631E-page 119
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