PIC18F45J10 FAMILY
TABLE 1-2:
PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
SPDIP,
SOIC, QFN
SSOP
Pin Name
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI
RC0
11
12
8
9
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
T1OSO
T1CKI
RC1/T1OSI/CCP2
RC1
I/O
I
I/O
ST
Analog
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
T1OSI
CCP2(2)
RC2/CCP1
RC2
13
14
10
11
I/O
I/O
ST
ST
Digital I/O.
CCP1
Capture 1 input/Compare 1 output/PWM1 output.
RC3/SCK1/SCL1
RC3
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
SCK1
SCL1
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
RC4/SDI1/SDA1
RC4
15
12
I/O
I
I/O
ST
ST
ST
Digital I/O.
SDI1
SDA1
SPI data in.
I2C data I/O.
RC5/SDO1
RC5
16
17
13
14
I/O
O
ST
—
Digital I/O.
SPI data out.
SDO1
RC6/TX/CK
RC6
I/O
O
I/O
ST
—
ST
Digital I/O.
TX
CK
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT).
RC7/RX/DT
RC7
18
15
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX
DT
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK).
VSS
VDD
8, 19 5, 16
P
P
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
20
6
17
3
VDDCORE/VCAP
VDDCORE
VCAP
P
P
—
—
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39682E-page 15
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