PIC18F45J10 FAMILY
FIGURE 1-2:
Table Pointer<21>
inc/dec logic
21
20
8
PCLATU PCLATH
PIC18F44J10/45J10 (40/44-PIN) BLOCK DIAGRAM
Data Bus<8>
Data Latch
Data Memory
(3.9 Kbytes)
Address Latch
12
Data Address<12>
4
BSR
12
FSR0
FSR1
FSR2
inc/dec
logic
4
Access
Bank
12
PORTA
RA0/AN0
RA1/AN1
RA2/AN2/V
REF
-/CV
REF
RA3/AN3/V
REF
+
RA5/AN4/SS1/C2OUT
8
PCU PCH PCL
Program Counter
31 Level Stack
PORTB
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2
(1)
RB4/KBI0/AN11
RB5/KBI1/T0CKI/C1OUT
RB6/KBI2/PGC
RB7/KBI3/PGD
Address Latch
Program Memory
(16/32 Kbytes)
Data Latch
8
STKPTR
Table Latch
ROM Latch
Instruction Bus <16>
IR
Address
Decode
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
(1)
RC2/CCP1/P1A
RC3/SCK1/SCL1
RC4/SDI1/SDA1
RC5/SDO1
RC6/TX/CK
RC7/RX/DT
Instruction
Decode and
Control
State Machine
Control Signals
8
PRODH PRODL
3
BITOP
8
8 x 8 Multiply
8
W
8
8
ALU<8>
8
PORTE
Precision
Band Gap
Reference
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
8
8
PORTD
RD0/PSP0/SCK2/SCL2
RD1/PSP1/SDI2/SDA2
RD2/PSP2/SDO2
RD3/PSP3/SS2
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
V
DDCORE
OSC1
OSC2
T1OSI
T1OSO
MCLR
V
DD
, V
SS
Internal
Oscillator
Block
INTRC
Oscillator
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Single-Supply
Programming
In-Circuit
Debugger
Brown-out
(2)
Reset
Fail-Safe
Clock Monitor
BOR
(2)
Timer0
Timer1
Timer2
ADC
10-Bit
Comparator
ECCP1
CCP2
MSSP
EUSART
Note
1:
2:
CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set.
Brown-out Reset is not available in PIC18LF2XJ10/4XJ10 devices.
©
2009 Microchip Technology Inc.
DS39682E-page 11
MICROCHIP [ MICROCHIP TECHNOLOGY ]
