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PIC18F24J10-I/SO 参数 Datasheet PDF下载

PIC18F24J10-I/SO图片预览
型号: PIC18F24J10-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能, RISC微控制器 [28/40/44-Pin High-Performance, RISC Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 368 页 / 5652 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F45J10 FAMILY  
1. Configure the EUSART for the desired mode.  
17.2.5  
BREAK CHARACTER SEQUENCE  
2. Set the TXEN and SENDB bits to set up the  
Break character.  
The EUSART module has the capability of sending the  
special Break character sequences that are required by  
the LIN/J2602 support standard. The Break character  
transmit consists of a Start bit, followed by twelve ‘0’  
bits and a Stop bit. The frame Break character is sent  
whenever the SENDB and TXEN bits (TXSTA<3> and  
TXSTA<5>) are set while the Transmit Shift register is  
loaded with data. Note that the value of data written to  
TXREG will be ignored and all ‘0’s will be transmitted.  
3. Load the TXREG with a dummy character to  
initiate transmission (the value is ignored).  
4. Write ‘55h’ to TXREG to load the Sync character  
into the transmit FIFO buffer.  
5. After the Break has been sent, the SENDB bit is  
reset by hardware. The Sync character now  
transmits in the preconfigured mode.  
The SENDB bit is automatically reset by hardware after  
the corresponding Stop bit is sent. This allows the user  
to preload the transmit FIFO with the next transmit byte  
following the Break character (typically, the Sync  
character in the LIN/J2602 support).  
When the TXREG becomes empty, as indicated by the  
TXIF, the next data byte can be written to TXREG.  
17.2.6  
RECEIVING A BREAK CHARACTER  
The Enhanced USART module can receive a Break  
character in two ways.  
Note that the data value written to the TXREG for the  
Break character is ignored. The write simply serves the  
purpose of initiating the proper sequence.  
The first method forces configuration of the baud rate  
at a frequency of 9/13 the typical speed. This allows for  
the Stop bit transition to be at the correct sampling loca-  
tion (13 bits for Break versus Start bit and 8 data bits for  
typical data).  
The TRMT bit indicates when the transmit operation is  
active or Idle, just as it does during normal transmis-  
sion. See Figure 17-10 for the timing of the Break  
character sequence.  
The second method uses the auto-wake-up feature  
described in Section 17.2.4 “Auto-Wake-up on Sync  
Break Character”. By enabling this feature, the  
EUSART will sample the next two transitions on RX/DT,  
cause an RCIF interrupt and receive the next data byte  
followed by another interrupt.  
17.2.5.1  
Break and Sync Transmit Sequence  
The following sequence will send a message frame  
header made up of a Break, followed by an Auto-Baud  
Sync byte. This sequence is typical of a LIN bus  
master.  
Note that following a Break character, the user will  
typically want to enable the Auto-Baud Rate Detect  
feature. For both methods, the user can set the ABD bit  
once the TXIF interrupt is observed.  
FIGURE 17-10:  
SEND BREAK CHARACTER SEQUENCE  
Write to TXREG  
Dummy Write  
BRG Output  
(Shift Clock)  
TX (pin)  
Start Bit  
Bit 0  
Bit 1  
Break  
Bit 11  
Stop Bit  
TXIF bit  
(Transmit Buffer  
Reg. Empty Flag)  
TRMT bit  
(Transmit Shift  
Reg. Empty Flag)  
SENDB sampled here  
Auto-Cleared  
SENDB  
(Transmit Shift  
Reg. Empty Flag)  
DS39682E-page 208  
© 2009 Microchip Technology Inc.  
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