PIC18F45J10 FAMILY
To set up a Synchronous Slave Transmission:
17.4 EUSART Synchronous
Slave Mode
1. Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is sup-
plied externally at the CK pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any low-power mode.
2. Clear bits, CREN and SREN.
3. If interrupts are desired, set enable bit, TXIE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting enable bit,
TXEN.
17.4.1
EUSART SYNCHRONOUS
SLAVE TRANSMISSION
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep
mode.
7. Start transmission by loading data to the TXREG
register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREG
register.
c) Flag bit, TXIF, will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit, TXIF, will now be
set.
e) If enable bit, TXIE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
TABLE 17-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
TMR0IF
CCP1IF
INT0IF
RBIF
47
49
49
49
49
49
49
49
49
49
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
SSP1IF
SSP1IE
SSP1IP
ADDEN
TMR2IF TMR1IF
PIE1
TXIE
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
TXIP
RCSTA
TXREG
TXSTA
CREN
FERR
OERR
RX9D
EUSART Transmit Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON ABDOVF
RCIDL
ABDEN
SPBRGH
SPBRG
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.
DS39682E-page 212
© 2009 Microchip Technology Inc.
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