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PIC18F2450-I/SO 参数 Datasheet PDF下载

PIC18F2450-I/SO图片预览
型号: PIC18F2450-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚,高性能, 12 MIPS ,增强型闪存, USB微控制器采用纳瓦技术 [28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 320 页 / 5591 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2450/4450  
6.2.2  
TABLE LATCH REGISTER (TABLAT)  
6.2.4  
TABLE POINTER BOUNDARIES  
The Table Latch (TABLAT) is an 8-bit register mapped  
into the SFR space. The Table Latch register is used to  
hold 8-bit data during data transfers between program  
memory and data RAM.  
TBLPTR is used in reads, writes and erases of the  
Flash program memory.  
When a TBLRDis executed, all 22 bits of the TBLPTR  
determine which byte is read from program memory  
into TABLAT.  
6.2.3  
TABLE POINTER REGISTER  
(TBLPTR)  
When a TBLWTis executed, the four LSbs of the Table  
Pointer register (TBLPTR<3:0>) determine which of the  
16 program memory holding registers is written to.  
When the timed write to program memory begins (via  
the WR bit), the 16 MSbs of the TBLPTR  
(TBLPTR<21:4>) determine which program memory  
block of 16 bytes is written to. For more detail, see  
Section 6.5 “Writing to Flash Program Memory”.  
The Table Pointer (TBLPTR) register addresses a byte  
within the program memory. The TBLPTR is comprised  
of three SFR registers: Table Pointer Upper Byte, Table  
Pointer High Byte and Table Pointer Low Byte  
(TBLPTRU:TBLPTRH:TBLPTRL). These three registers  
join to form a 22-bit wide pointer. The low-order 21 bits  
allow the device to address up to 2 Mbytes of program  
memory space. The 22nd bit allows access to the device  
ID, the user ID and the Configuration bits.  
When an erase of program memory is executed, the  
16 MSbs of the Table Pointer register (TBLPTR<21:6>)  
point to the 64-byte block that will be erased. The Least  
Significant bits (TBLPTR<5:0>) are ignored.  
The Table Pointer, TBLPTR, is used by the TBLRDand  
TBLWTinstructions. These instructions can update the  
TBLPTR in one of four ways based on the table opera-  
tion. These operations are shown in Table 6-1. These  
operations on the TBLPTR only affect the low-order  
21 bits.  
Figure 6-3 describes the relevant boundaries of the  
TBLPTR based on Flash program memory operations.  
TABLE 6-1:  
Example  
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS  
Operation on Table Pointer  
TBLRD*  
TBLWT*  
TBLPTR is not modified  
TBLRD*+  
TBLWT*+  
TBLPTR is incremented after the read/write  
TBLPTR is decremented after the read/write  
TBLPTR is incremented before the read/write  
TBLRD*-  
TBLWT*-  
TBLRD+*  
TBLWT+*  
FIGURE 6-3:  
TABLE POINTER BOUNDARIES BASED ON OPERATION  
21  
16 15  
TBLPTRH  
8
7
TBLPTRL  
0
TBLPTRU  
TABLE ERASE  
TBLPTR<21:6>  
TABLE WRITE – TBLPTR<21:4>  
TABLE READ – TBLPTR<21:0>  
DS39760A-page 76  
Advance Information  
© 2006 Microchip Technology Inc.  
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