PIC18F2450/4450
FIGURE 2-3:
EXTERNAL CLOCK INPUT
2.2.4
PLL FREQUENCY MULTIPLIER
OPERATION (HS OSC
CONFIGURATION)
PIC18F2450/4450 devices include a Phase Locked
Loop (PLL) circuit. This is provided specifically for USB
applications with lower speed oscillators and can also
be used as a microcontroller clock source.
OSC1
Clock from
Ext. System
The PLL is enabled in HSPLL, XTPLL, ECPLL and
ECPIO Oscillator modes. It is designed to produce a
fixed 96 MHz reference clock from a fixed 4 MHz input.
The output can then be divided and used for both the
USB and the microcontroller core clock. Because the
PLL has a fixed frequency input and output, there are
eight prescaling options to match the oscillator input
frequency to the PLL.
PIC18FXXXX
(HS Mode)
OSC2
Open
2.2.3
EXTERNAL CLOCK INPUT
The EC, ECIO, ECPLL and ECPIO Oscillator modes
require an external clock source to be connected to the
OSC1 pin. There is no oscillator start-up time required
after a Power-on Reset or after an exit from Sleep
mode.
There is also a separate postscaler option for deriving
the microcontroller clock from the PLL. This allows the
USB peripheral and microcontroller to use the same
oscillator input and still operate at different clock
speeds. In contrast to the postscaler for XT, HS and EC
modes, the available options are 1/2, 1/3, 1/4 and 1/6
of the PLL output.
In the EC and ECPLL Oscillator modes, the oscillator
frequency divided by 4 is available on the OSC2 pin.
This signal may be used for test purposes or to
synchronize other logic. Figure 2-4 shows the pin
connections for the EC Oscillator mode.
The HSPLL, ECPLL and ECPIO modes make use of
the HS mode oscillator for frequencies up to 48 MHz.
The prescaler divides the oscillator input by up to 12 to
produce the 4 MHz drive for the PLL. The XTPLL mode
can only use an input frequency of 4 MHz which drives
the PLL directly.
FIGURE 2-4:
EXTERNAL CLOCK
INPUT OPERATION
(EC AND ECPLL
CONFIGURATION)
FIGURE 2-6:
PLL BLOCK DIAGRAM
(HS MODE)
OSC1/CLKI
Clock from
Ext. System
PIC18FXXXX
OSC2/CLKO
FOSC/4
HS/EC/ECIO/XT Oscillator Enable
PLL Enable
(from CONFIG1H Register)
The ECIO and ECPIO Oscillator modes function like the
EC and ECPLL modes, except that the OSC2 pin
becomes an additional general purpose I/O pin. The I/O
pin becomes bit 6 of PORTA (RA6). Figure 2-5 shows
the pin connections for the ECIO Oscillator mode.
OSC2
Phase
Oscillator
and
Comparator
FIN
OSC1
FOUT
Prescaler
FIGURE 2-5:
EXTERNAL CLOCK
INPUT OPERATION
(ECIO AND ECPIO
CONFIGURATION)
Loop
Filter
VCO
÷24
SYSCLK
OSC1/CLKI
PIC18FXXXX
I/O (OSC2)
Clock from
Ext. System
RA6
The internal postscaler for reducing clock frequency in
XT and HS modes is also available in EC and ECIO
modes.
DS39760A-page 26
Advance Information
© 2006 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
