PIC18F2450/4450
REGISTER 18-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-1
R/P-0
R/P-0
ICPRT(1)
U-0
—
R/P-0
R/P-1
LVP
U-0
—
R/P-1
DEBUG
XINST
BBSIZ
STVREN
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7
bit 6
bit 5
DEBUG: Background Debugger Enable bit
1= Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0= Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
XINST: Extended Instruction Set Enable bit
1= Instruction set extension and Indexed Addressing mode enabled
0= Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
ICPRT: Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit(1)
1= ICPORT enabled
0= ICPORT disabled
bit 4
bit 3
Unimplemented: Read as ‘0’
BBSIZ: Boot Block Size Select bit
1= 2 kW Boot Block size
0= 1 kW Boot Block size
bit 2
LVP: Single-Supply ICSP™ Enable bit
1= Single-Supply ICSP enabled
0= Single-Supply ICSP disabled
bit 1
bit 0
Unimplemented: Read as ‘0’
STVREN: Stack Full/Underflow Reset Enable bit
1= Stack full/underflow will cause Reset
0= Stack full/underflow will not cause Reset
Note 1: Available only on PIC18F4450 devices in 44-pin TQFP packages. Always leave this bit clear in all other
devices.
DS39760A-page 196
Advance Information
© 2006 Microchip Technology Inc.
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