PIC18F45J10 FAMILY
TABLE 6-3:
REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10) (CONTINUED)
Value on
POR, BOR on page:
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EECON2
EECON1
IPR3
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
EUSART Receive Register
0000 0000 49, 198
0000 0000 49, 198
0000 0000 49, 205
xxxx xxxx 49, 203
0000 0010 49, 196
0000 000x 49, 195
0000 0000 49, 72
---0 x00- 49, 74
11-- ---- 49, 94
00-- ---- 49, 90
00-- ---- 49, 92
11-- 1--1 49, 93
00-- 0--0 49, 89
00-- 0--0 49, 91
1111 1111 49, 92
0000 0000 49, 88
0000 0000 49, 91
0000 -111 50, 112
1111 1111 50, 107
1111 1111 50, 104
1111 1111 50, 101
--1- 1111 50, 98
xxxx xxxx 50, 158
---- -xxx 50, 110
EUSART Transmit Register
CSRC
SPEN
TX9
RX9
TXEN
SREN
SYNC
CREN
SENDB
ADDEN
BRGH
FERR
TRMT
OERR
TX9D
RX9D
EEPROM Control Register 2 (not a physical register)
—
—
—
—
FREE
WRERR
—
WREN
—
WR
—
—
SSP2IP
SSP2IF
SSP2IE
OSCFIP
OSCFIF
OSCFIE
PSPIP(2)
PSPIF(2)
PSPIE(2)
IBF
BCL2IP
BCL2IF
BCL2IE
CMIP
CMIF
CMIE
ADIP
—
—
—
PIR3
—
—
—
—
—
PIE3
—
—
—
—
—
—
IPR2
—
—
BCL1IP
BCL1IF
BCL1IE
SSP1IP
SSP1IF
SSP1IE
—
—
—
CCP2IP
CCP2IF
CCP2IE
TMR1IP
TMR1IF
TMR1IE
TRISE0
PIR2
—
—
—
—
PIE2
—
—
—
—
IPR1
RCIP
RCIF
RCIE
IBOV
TXIP
TXIF
TXIE
PSPMODE
CCP1IP
CCP1IF
CCP1IE
TRISE2
TMR2IP
TMR2IF
TMR2IE
TRISE1
PIR1
ADIF
PIE1
ADIE
TRISE(2)
TRISD(2)
TRISC
TRISB
TRISA
SSP2BUF
LATE(2)
OBF
PORTD Data Direction Control Register
PORTC Data Direction Control Register
PORTB Data Direction Control Register
—
—
TRISA5
—
—
TRISA3
—
TRISA2
TRISA1
TRISA0
MSSP2 Receive Buffer/Transmit Register
—
—
—
PORTE Data Latch Register
(Read and Write to Data Latch)
LATD(2)
LATC
PORTD Data Latch Register (Read and Write to Data Latch)
PORTC Data Latch Register (Read and Write to Data Latch)
PORTB Data Latch Register (Read and Write to Data Latch)
xxxx xxxx 50, 107
xxxx xxxx 50, 104
xxxx xxxx 50, 101
--xx xxxx 50, 98
0000 0000 50, 158
LATB
LATA
—
—
PORTA Data Latch Register (Read and Write to Data Latch)
SSP2ADD
SSP2STAT
MSSP2 Address Register in I2C™ Slave mode. MSSP2 Baud Rate Reload Register in I2C Master mode.
SMP
CKE
D/A
P
S
R/W
SSPM2
PEN
UA
BF
0000 0000 50, 150,
160
SSP2CON1
SSP2CON2
WCOL
SSPOV
ACKSTAT
SSPEN
ACKDT
CKP
SSPM3
RCEN
SSPM1
RSEN
SSPM0
0000 0000 50, 151,
161
GCEN
GCEN
—
ACKEN
SEN
SEN
RE0(2)
RD0
RC0
RB0
0000 0000 50, 164
0000 0000 48, 163
---- -xxx 50, 110
xxxx xxxx 50, 107
xxxx xxxx 50, 104
xxxx xxxx 50, 101
--0- 0000 50, 98
ACKSTAT ADMSK5(3) ADMSK4(3) ADMSK3(3) ADMSK2(3) ADMSK1(3)
PORTE(2)
PORTD(2)
PORTC
PORTB
—
—
—
—
RE2(2)
RD2
RC2
RB2
RE1(2)
RD1
RC1
RB1
RD7
RC7
RB7
—
RD6
RC6
RB6
—
RD5
RC5
RB5
RA5
RD4
RC4
RB4
—
RD3
RC3
RB3
RA3
PORTA
RA2
RA1
RA0
Legend:
Note 1:
2:
x= unknown, u= unchanged, -= unimplemented, q= value depends on condition
See Section 5.4 “Brown-out Reset (BOR) (PIC18F2XJ10/4XJ10 Devices Only)”.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 16.4.3.2 “Address
Masking” for details.
3:
DS39682E-page 64
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
