PIC18F45J10 FAMILY
TABLE 6-3:
REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10) (CONTINUED)
Value on
POR, BOR on page:
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0H
TMR0L
Timer0 Register High Byte
Timer0 Register Low Byte
0000 0000 48, 117
xxxx xxxx 48, 117
1111 1111 48, 115
0--- q-00 32, 48
--- ---0 48, 242
0-11 11q0 42, 46, 94
xxxx xxxx 48, 124
xxxx xxxx 48, 124
T0CON
OSCCON
WDTCON
RCON
TMR0ON
IDLEN
—
T08BIT
—
T0CS
—
T0SE
—
PSA
OSTS
—
T0PS2
—
T0PS1
SCS1
—
T0PS0
SCS0
—
—
—
—
SWDTEN
BOR(1)
IPEN
—
CM
RI
TO
PD
POR
TMR1H
TMR1L
Timer1 Register High Byte
Timer1 Register Low Byte
T1CON
TMR2
RD16
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR2ON
TMR1CS
T2CKPS1
TMR1ON 0000 0000 48, 119
0000 0000 48, 126
Timer2 Register
PR2
Timer2 Period Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
MSSP1 Receive Buffer/Transmit Register
1111 1111 48, 126
T2CON
SSP1BUF
SSP1ADD
SSP1STAT
—
T2CKPS0 -000 0000 48, 125
xxxx xxxx 48, 158
MSSP1 Address Register in I2C™ Slave mode. MSSP1 Baud Rate Reload Register in I2C Master mode.
0000 0000 48, 159
SMP
CKE
D/A
P
S
R/W
SSPM2
PEN
UA
BF
0000 0000 48, 150,
160
SSP1CON1
SSP1CON2
WCOL
SSPOV
ACKSTAT
SSPEN
ACKDT
CKP
SSPM3
RCEN
SSPM1
RSEN
SSPM0
0000 0000 48, 151,
161
GCEN
GCEN
ACKEN
SEN
SEN
0000 0000 48, 162
0000 0000 48, 163
xxxx xxxx 48, 223
xxxx xxxx 48, 223
ACKSTAT ADMSK5(3) ADMSK4(3) ADMSK3(3) ADMSK2(3) ADMSK1(3)
ADRESH
ADRESL
A/D Result Register High Byte
A/D Result Register Low Byte
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
ADCAL
—
—
—
—
CHS3
VCFG1
ACQT2
CHS2
VCFG0
ACQT1
CHS1
PCFG3
ACQT0
CHS0
PCFG2
ADCS2
GO/DONE
PCFG1
ADON
PCFG0
ADCS0
0-00 0000 48, 218
--00 0qqq 48, 218
0-00 0000 48, 218
xxxx xxxx 49, 128
xxxx xxxx 49, 128
ADFM
ADCS1
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
CCP1CON
CCPR2H
CCPR2L
P1M1(2)
P1M0(2)
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0 0000 0000 49, 128,
xxxx xxxx 49, 128
Capture/Compare/PWM Register 2 High Byte
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx 49, 128
CCP2CON
BAUDCON
ECCP1DEL
ECCP1AS
CVRCON
CMCON
—
—
DC2B1
—
PDC5(2)
ECCPAS1
CVRR
DC2B0
SCKP
PDC4(2)
ECCPAS0
CVRSS
C1INV
CCP2M3
BRG16
PDC3(2)
PSSAC1
CVR3
CCP2M2
—
PDC2(2)
PSSAC0
CVR2
CM2
CCP2M1
WUE
PDC1(2)
CCP2M0 --00 0000 49, 128
ABDOVF
PRSEN
ECCPASE
CVREN
C2OUT
RCIDL
ABDEN
PDC0(2)
01-0 0-00 49, 196
0000 0000 49, 144
PDC6(2)
ECCPAS2
CVROE
C1OUT
PSSBD1(2) PSSBD0(2) 0000 0000 49, 146
CVR1
CM1
CVR0
CM0
0000 0000 49, 232
0000 0111 49, 226
C2INV
CIS
Legend:
Note 1:
2:
x= unknown, u= unchanged, -= unimplemented, q= value depends on condition
See Section 5.4 “Brown-out Reset (BOR) (PIC18F2XJ10/4XJ10 Devices Only)”.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 16.4.3.2 “Address
Masking” for details.
3:
© 2009 Microchip Technology Inc.
DS39682E-page 63
MICROCHIP [ MICROCHIP ]
