PIC18F45J10 FAMILY
TABLE 6-3:
File Name
TOSU
REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10)
Value on
POR, BOR on page:
Details
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 47, 53
0000 0000 47, 53
0000 0000 47, 53
00-0 0000 47, 54
---0 0000 47, 53
0000 0000 47, 53
0000 0000 47, 53
--00 0000 47, 74
0000 0000 47, 74
0000 0000 47, 74
0000 0000 47, 74
xxxx xxxx 47, 81
xxxx xxxx 47, 81
0000 000x 47, 85
TOSH
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
TOSL
STKPTR
PCLATU
PCLATH
PCL
STKFUL
—
STKUNF
—
—
—
Return Stack Pointer
Holding Register for PC<20:16>
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
—
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
INTCON2
INTCON3
INDF0
RBPU
INTEDG0
INT1IP
INTEDG1
—
INTEDG2
INT2IE
—
TMR0IP
—
—
RBIP
1111 -1-1 47, 86
11-0 0-00 47, 87
INT2IP
INT1IE
INT2IF
INT1IF
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
N/A
N/A
N/A
N/A
47, 67
47, 67
47, 67
47, 67
47, 67
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
PREINC0
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
FSR0H
FSR0L
WREG
INDF1
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte
---- xxxx 47, 67
xxxx xxxx 47, 67
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
xxxx xxxx
N/A
47
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
47, 67
47, 67
47, 67
47, 67
47, 67
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
N/A
PREINC1
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
FSR1H
FSR1L
BSR
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte
---- xxxx 47, 67
xxxx xxxx 47, 67
---- 0000 47, 58
Indirect Data Memory Address Pointer 1 Low Byte
—
—
—
—
Bank Select Register
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
N/A
N/A
N/A
N/A
48, 67
48, 67
48, 67
48, 67
48, 67
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
PREINC2
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
FSR2H
FSR2L
STATUS
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte
---- xxxx 48, 67
xxxx xxxx 48, 67
---x xxxx 48, 65
Indirect Data Memory Address Pointer 2 Low Byte
—
—
—
N
OV
Z
DC
C
Legend:
Note 1:
2:
x= unknown, u= unchanged, -= unimplemented, q= value depends on condition
See Section 5.4 “Brown-out Reset (BOR) (PIC18F2XJ10/4XJ10 Devices Only)”.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
3:
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 16.4.3.2 “Address
Masking” for details.
DS39682E-page 62
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
