PIC18F45J10 FAMILY
If the A/D is expected to operate while the device is in
18.7 A/D Converter Calibration
a
power-managed mode, the ACQT<2:0> and
The A/D converter in the PIC18F45J10 family of
devices includes a self-calibration feature which com-
pensates for any offset generated within the module.
The calibration process is automated and is initiated by
setting the ADCAL bit (ADCON0<7>). The next time
the GO/DONE bit is set, the module will perform a
“dummy” conversion (that is, with reading none of the
input channels) and store the resulting value internally
to compensate for offset. Thus, subsequent offsets will
be compensated.
ADCS<2:0> bits in ADCON2 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-managed mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been com-
pleted. If desired, the device may be placed into the
corresponding power-managed Idle mode during the
conversion.
The calibration process assumes that the device is in a
relatively steady-state operating condition. If A/D
calibration is used, it should be performed after each
device Reset or if there are other major changes in
operating conditions.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in the Sleep mode requires the A/D RC clock
to be selected. If bits, ACQT<2:0>, are set to ‘000’ and
a conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode. The IDLEN and
SCS bits in the OSCCON register must have already
been cleared prior to starting the conversion.
18.8 Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
TABLE 18-2: REGISTERS ASSOCIATED WITH A/D OPERATION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
PIE1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
TXIE
TXIP
—
RBIE
TMR0IF
CCP1IF
CCP1IE
CCP1IP
—
INT0IF
TMR2IF
TMR2IE
TMR2IP
—
RBIF
47
49
49
49
49
49
49
48
48
48
48
48
50
50
50
50
50
50
50
50
PSPIF(1)
PSPIE(1)
PSPIP(1)
OSCFIF
OSCFIE
OSCFIP
ADIF
ADIE
ADIP
CMIF
CMIE
CMIP
RCIF
RCIE
RCIP
—
SSP1IF
SSP1IE
SSP1IP
BCL1IF
BCL1IE
BCL1IP
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
IPR1
PIR2
PIE2
—
—
—
—
IPR2
—
—
—
—
ADRESH A/D Result Register High Byte
ADRESL A/D Result Register Low Byte
ADCON0
ADCON1
ADCON2
PORTA
TRISA
ADCAL
—
—
—
CHS3
VCFG1
ACQT2
RA5
CHS2
VCFG0
ACQT1
—
CHS1
PCFG3
ACQT0
RA3
CHS0 GO/DONE ADON
PCFG2
ADCS2
RA2
PCFG1
ADCS1
RA1
PCFG0
ADCS0
RA0
ADFM
—
—
—
—
—
TRISA5
RB5
—
TRISA3
RB3
TRISA2
RB2
TRISA1
RB1
TRISA0
RB0
PORTB
TRISB
RB7
RB6
RB4
PORTB Data Direction Control Register
PORTB Data Latch Register (Read and Write to Data Latch)
LATB
PORTE(1)
TRISE(1)
LATE(1)
—
IBF
—
—
OBF
—
—
IBOV
—
—
PSPMODE
—
—
—
—
RE2
RE1
RE0
TRISE2
TRISE1
TRISE0
PORTE Data Latch Register
(Read and Write to Data Latch)
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.
© 2009 Microchip Technology Inc.
DS39682E-page 223
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