欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F25J10-I/SS 参数 Datasheet PDF下载

PIC18F25J10-I/SS图片预览
型号: PIC18F25J10-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能, RISC微控制器 [28/40/44-Pin High-Performance, RISC Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 368 页 / 5652 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第220页浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第221页浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第222页浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第223页浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第225页浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第226页浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第227页浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第228页  
PIC18F45J10 FAMILY  
18.5 A/D Conversions  
18.6 Use of the ECCP2 Trigger  
Figure 18-3 shows the operation of the A/D converter  
after the GO/DONE bit has been set and the  
ACQT<2:0> bits are cleared. A conversion is started  
after the following instruction to allow entry into Sleep  
mode before the conversion begins.  
An A/D conversion can be started by the “Special Event  
Trigger” of the ECCP2 module. This requires that the  
CCP2M<3:0> bits (CCP2CON<3:0>) be programmed  
as ‘1011’ and that the A/D module is enabled (ADON  
bit is set). When the trigger occurs, the GO/DONE bit  
will be set, starting the A/D acquisition and conversion  
and the Timer1 (or Timer3) counter will be reset to zero.  
Timer1 (or Timer3) is reset to automatically repeat the  
A/D acquisition period with minimal software overhead  
(moving ADRESH/ADRESL to the desired location).  
The appropriate analog input channel must be selected  
and the minimum acquisition period is either timed by  
the user, or an appropriate TACQ time is selected before  
the Special Event Trigger sets the GO/DONE bit (starts  
a conversion).  
Figure 18-4 shows the operation of the A/D converter  
after the GO/DONE bit has been set, the ACQT<2:0>  
bits are set to ‘010’ and selecting a 4 TAD acquisition  
time before the conversion starts.  
Clearing the GO/DONE bit during a conversion will abort  
the current conversion. The A/D Result register pair will  
NOT be updated with the partially completed A/D  
conversion sample. This means the ADRESH:ADRESL  
registers will continue to contain the value of the last  
completed conversion (or the last value written to the  
ADRESH:ADRESL registers).  
If the A/D module is not enabled (ADON is cleared), the  
Special Event Trigger will be ignored by the A/D module  
but will still reset the Timer1 (or Timer3) counter.  
After the A/D conversion is completed or aborted, a  
2 TAD wait is required before the next acquisition can be  
started. After this wait, acquisition on the selected  
channel is automatically started.  
Note: The GO/DONE bit should NOT be set in  
the same instruction that turns on the A/D.  
FIGURE 18-3:  
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)  
TCY - TAD  
TAD8 TAD9 TAD10 TAD11  
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7  
b4  
b1  
b0  
b9  
b8  
b7  
b6  
b5  
b3  
b2  
Conversion starts  
Holding capacitor is disconnected from analog input (typically 100 ns)  
Set GO/DONE bit  
Next Q4: ADRESH/ADRESL is loaded, GO/DONE bit is cleared,  
ADIF bit is set, holding capacitor is connected to analog input.  
FIGURE 18-4:  
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)  
TAD Cycles  
TACQT Cycles  
7
8
9
10  
b1  
11  
b0  
1
2
3
4
1
2
3
4
5
6
b7  
b6  
b3  
b2  
b8  
b5  
b4  
b9  
Automatic  
Acquisition  
Time  
Conversion starts  
(Holding capacitor is disconnected)  
Set GO/DONE bit  
(Holding capacitor continues  
acquiring input)  
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,  
ADIF bit is set, holding capacitor is reconnected to analog input.  
DS39682E-page 222  
© 2009 Microchip Technology Inc.