PIC18F45J10 FAMILY
TABLE 15-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
RCON
PIR1
GIE/GIEH PEIE/GIEL
TMR0IE
CM
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
47
46
49
49
49
49
49
49
50
50
50
48
48
48
48
48
48
49
49
49
49
49
IPEN
—
BOR
(1)
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
CMIF
CMIE
CMIP
RCIF
RCIE
RCIP
—
TXIF
TXIE
TXIP
—
SSP1IF
SSP1IE
SSP1IP
BCL1IF
BCL1IE
BCL1IP
CCP1IF
CCP1IE
CCP1IP
—
TMR2IF
TMR2IE
TMR2IP
—
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
(1)
(1)
PIE1
IPR1
PIR2
OSCFIF
OSCFIE
OSCFIP
PIE2
—
—
—
—
IPR2
—
—
—
—
TRISB
TRISC
PORTB Data Direction Control Register
PORTC Data Direction Control Register
PORTD Data Direction Control Register
Timer1 Register Low Byte
(1)
TRISD
TMR1L
TMR1H
T1CON
TMR2
Timer1 Register High Byte
RD16
Timer2 Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
T1RUN
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
T2CON
PR2
—
Timer2 Period Register
CCPR1L
CCPR1H
CCP1CON
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
(1)
(1)
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
PSSAC1
CCP1M2 CCP1M1 CCP1M0
(1)
(1)
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0
PSSAC0 PSSBD1
PSSBD0
(1)
(1)
(1)
(1)
(1)
(1)
(1)
ECCP1DEL
PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.
DS39682E-page 148
© 2009 Microchip Technology Inc.
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