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PIC18F25J10-I/SS 参数 Datasheet PDF下载

PIC18F25J10-I/SS图片预览
型号: PIC18F25J10-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能, RISC微控制器 [28/40/44-Pin High-Performance, RISC Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 368 页 / 5652 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F45J10 FAMILY  
14.3.2  
TIMER1 MODE SELECTION  
14.3 Compare Mode  
Timer1 must be running in Timer mode or Synchro-  
nized Counter mode if the CCP module is using the  
compare feature. In Asynchronous Counter mode, the  
compare operation may not work.  
In Compare mode, the 16-bit CCPRx register value is  
constantly compared against the TMR1 register value.  
When a match occurs, the CCPx pin can be:  
• driven high  
• driven low  
14.3.3  
SOFTWARE INTERRUPT MODE  
• toggled (high-to-low or low-to-high)  
When the Generate Software Interrupt mode is chosen  
(CCPxM<3:0> = 1010), the corresponding CCPx pin is  
not affected. Only a CCP interrupt is generated, if  
enabled and the CCPxIE bit is set.  
• remain unchanged (that is, reflects the state of the  
I/O latch)  
The action on the pin is based on the value of the mode  
select bits (CCPxM<3:0>). At the same time, the inter-  
rupt flag bit, CCPxIF, is set.  
14.3.4  
SPECIAL EVENT TRIGGER  
Both CCP modules are equipped with a Special Event  
Trigger. This is an internal hardware signal generated  
in Compare mode to trigger actions by other modules.  
The Special Event Trigger is enabled by selecting  
the Compare Special Event Trigger mode  
(CCPxM<3:0> = 1011).  
14.3.1  
CCP PIN CONFIGURATION  
The user must configure the CCPx pin as an output by  
clearing the appropriate TRIS bit.  
Note:  
Clearing the CCP2CON register will force  
the RB3 or RC1 compare output latch  
(depending on device configuration) to the  
default low level. This is not the PORTB or  
PORTC I/O data latch.  
For either CCP module, the Special Event Trigger resets  
the Timer register pair for whichever timer resource is  
currently assigned as the module’s time base. This  
allows the CCPRx registers to serve as a Programmable  
Period register for either timer.  
The Special Event Trigger for CCP2 can also start an  
A/D conversion. In order to do this, the A/D converter  
must already be enabled.  
FIGURE 14-2:  
COMPARE MODE OPERATION BLOCK DIAGRAM  
Special Event Trigger  
(Timer1 Reset)  
Set CCP1IF  
CCPR1H  
CCPR1L  
CCP1 pin  
S
R
Q
Output  
Logic  
Compare  
Match  
Comparator  
TRIS  
Output Enable  
4
CCP1CON<3:0>  
TMR1H  
TMR1L  
Special Event Trigger  
(Timer1 Reset, A/D Trigger)  
Set CCP2IF  
CCP2 pin  
S
Q
Compare  
Match  
Output  
Logic  
Comparator  
R
TRIS  
Output Enable  
4
CCPR2H  
CCPR2L  
CCP2CON<3:0>  
DS39682E-page 130  
© 2009 Microchip Technology Inc.