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PIC18F8620-I/PT 参数 Datasheet PDF下载

PIC18F8620-I/PT图片预览
型号: PIC18F8620-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器和处理器外围集成电路PC时钟
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18FXX20  
During  
a
TBLWT cycle to an odd address  
6.2.2  
16-BIT WORD WRITE MODE  
(TBLPTR<0> = 1), the TABLAT data is presented on  
the upper byte of the AD15:AD0 bus. The contents of  
the holding latch are presented on the lower byte of the  
AD15:AD0 bus.  
Figure 6-2 shows an example of 16-bit Word Write  
mode for PIC18F8X20 devices. This mode is used for  
word-wide memories, which includes some of the  
EPROM and FLASH type memories. This mode allows  
opcode fetches and Table Reads from all forms of  
16-bit memory, and Table Writes to any type of  
word-wide external memories. This method makes a  
distinction between TBLWT cycles to even or odd  
addresses.  
The WRH signal is strobed for each write cycle; the  
WRL pin is unused. The signal on the BA0 pin indicates  
the LSbit of TBLPTR, but it is left unconnected. Instead,  
the UB and LB signals are active to select both bytes.  
The obvious limitation to this method is that the Table  
Write must be done in pairs on a specific word  
boundary to correctly write a word location.  
During  
a
TBLWT cycle to an even address  
(TBLPTR<0> = 0), the TABLAT data is transferred to a  
holding latch and the external address data bus is  
tri-stated for the data portion of the bus cycle. No write  
signals are activated.  
FIGURE 6-2:  
16-BIT WORD WRITE MODE EXAMPLE  
PIC18F8X20  
AD<7:0>  
A<20:1>  
D<15:0>  
JEDEC Word  
373  
373  
A<x:0>  
EPROM Memory  
D<15:0>  
CE  
(1)  
OE  
WR  
AD<15:8>  
ALE  
A<19:16>  
CE  
OE  
WRH  
Address Bus  
Data Bus  
Control Lines  
Note 1: This signal only applies to Table Writes. See Section 5.1 (Table Reads and Writes).  
DS39609A-page 74  
Advance Information  
2003 Microchip Technology Inc.  
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