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PIC18F8620-I/PT 参数 Datasheet PDF下载

PIC18F8620-I/PT图片预览
型号: PIC18F8620-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器和处理器外围集成电路PC时钟
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18FXX20  
FLASH and SRAM devices use different control signal  
combinations to implement Byte Select mode. JEDEC  
standard FLASH memories require that a controller I/O  
port pin be connected to the memory’s BYTE/WORD  
pin to provide the select signal. They also use the BA0  
signal from the controller as a byte address. JEDEC  
standard static RAM memories, on the other hand, use  
the UB or LB signals to select the byte.  
6.2.3  
16-BIT BYTE SELECT MODE  
Figure 6-3 shows an example of 16-bit Byte Select  
mode for PIC18F8X20 devices. This mode allows  
Table Write operations to word-wide external memories  
with byte-selection capability. This generally includes  
both word-wide FLASH and SRAM devices.  
During a TBLWTcycle, the TABLAT data is presented  
on the upper and lower byte of the AD15:AD0 bus. The  
WRH signal is strobed for each write cycle; the WRL  
pin is not used. The BA0 or UB/LB signals are used to  
select the byte to be written, based on the Least  
Significant bit of the TBLPTR register.  
FIGURE 6-3:  
16-BIT BYTE SELECT MODE EXAMPLE  
PIC18F8X20  
A<20:1>  
AD<7:0>  
373  
373  
JEDEC Word  
A<x:1>  
FLASH Memory  
D<15:0>  
D<15:0>  
(2)  
138  
CE  
A0  
AD<15:8>  
(1)  
ALE  
A<19:16>  
OE  
BYTE/WORD OE WR  
WRH  
A<20:1>  
WRL  
JEDEC Word  
SRAM Memory  
A<x:1>  
BA0  
I/O  
D<15:0>  
D<15:0>  
CE  
LB  
UB  
LB  
UB  
(1)  
OE WR  
Address Bus  
Data Bus  
Control Lines  
Note 1: This signal only applies to Table Writes. See Section 5.1 (Table Reads and Writes).  
2: De-multiplexing is only required when multiple memory devices are accessed.  
2003 Microchip Technology Inc.  
Advance Information  
DS39609A-page 75