PIC18FXX20
EXAMPLE 5-3:
PROGRAM_MEMORY
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
EECON1,EEPGD
EECON1,CFGS
EECON1,WREN
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
; point to FLASH program memory
; access FLASH program memory
; enable write to memory
; disable interrupts
Required
Sequence
; write 55H
; write AAH
; start program (CPU stall)
NOP
BSF
INTCON,GIE
; re-enable interrupts
; loop until done
DECFSZ COUNTER_HI
BRA PROGRAM_LOOP
BCF
EECON1,WREN
; disable write to memory
Time-out Reset during normal operation. In these situ-
ations, users can check the WRERR bit and rewrite the
location.
5.5.2
WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
5.5.4
PROTECTION AGAINST SPURIOUS
WRITES
To protect against spurious writes to FLASH program
memory, the write initiate sequence must also be fol-
lowed. See “Special Features of the CPU”
(Section 23.0) for more detail.
5.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected RESET, the memory
location just programmed should be verified and repro-
grammed if needed.The WRERR bit is set when a write
operation is interrupted by a MCLR Reset, or a WDT
5.6
FLASH Program Operation During
Code Protection
See “Special Features of the CPU” (Section 23.0) for
details on code protection of FLASH program memory.
TABLE 5-2:
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Value on:
POR,
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
Program Memory Table Pointer Upper Byte
(TBLPTR<20:16>)
TBLPTRU
—
—
bit21
--00 0000 --00 0000
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>)
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
TABLAT
INTCON
EECON2
EECON1
Program Memory Table Latch
GIE/GIEH PEIE/GIEL TMR0IE
EEPROM Control Register2 (not a physical register)
INTE
RBIE
TMR0IF
INTF
RBIF
—
—
EEPGD
CFGS
CMIP
—
FREE
EEIP
WRERR WREN
BCLIP
WR
TMR3IP
RD
CCP2IP
xx-0 x000 uu-0 u000
---1 1111 ---1 1111
---0 0000 ---0 0000
LVDIP
IPR2
—
—
PIR2
PIE2
—
—
CMIF
CMIE
—
—
EEIF
EEIE
BCLIF
BCLIE
LVDIF
LVDIE
TMR3IF
TMR3IE
CCP2IF
CCP2IE ---0 0000 ---0 0000
Legend: x= unknown, u= unchanged, r= reserved, -= unimplemented, read as '0'.
Shaded cells are not used during FLASH/EEPROM access.
DS39609A-page 70
Advance Information
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
