PIC18FXX20
USART1, PIE3<4> for USART2). Flag bit TXxIF will be
set, regardless of the state of enable bit TXxIE, and
cannot be cleared in software. It will reset only when
new data is loaded into the TXREGx register. While flag
bit TXxIF indicates the status of the TXREGx register,
another bit TRMT (TXSTAx<1>) shows the status of the
TSR register. TRMT is a read only bit, which is set
when the TSR is empty. No interrupt logic is tied to this
bit, so the user has to poll this bit in order to determine
if the TSR register is empty. The TSR is not mapped in
data memory, so it is not available to the user.
18.3 USART Synchronous Master
Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTAx<4>). In
addition, enable bit SPEN (RCSTAx<7>) is set in order
to configure the appropriate I/O pins to CK (clock) and
DT (data) lines, respectively. The Master mode indi-
cates that the processor transmits the master clock on
the CK line. The Master mode is entered by setting bit
CSRC (TXSTAx<7>).
To set up a Synchronous Master Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 18.1).
18.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. If interrupts are desired, set enable bit TXxIE in
The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(serial) Shift Register (TSR). The shift register obtains
its data from the read/write transmit buffer register,
TXREG. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREGx (if available). Once the
TXREGx register transfers the data to the TSR register
(occurs in one TCYCLE), the TXREGx is empty and
interrupt bit TXxIF (PIR1<4> for USART1, PIR3<4> for
USART2) is set. The interrupt can be enabled/disabled
by setting/clearing enable bit TXxIE (PIE1<4> for
the appropriate PIE register.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREGx register.
Note: TXIF is not cleared immediately upon load-
ing data into the transmit buffer TXREG.
The flag bit becomes valid in the second
instruction cycle following the load
instruction.
TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on
POR,
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
INTCON
GIE/
PEIE/
GIEL
ADIF
ADIE
ADIP
—
TMR0IE INT0IE
RBIE
TMR0IF
CCP1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
INT0IF
RBIF
0000 0000
0000 0000
GIEH
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
PSPIF
PSPIE
PSPIP
—
—
—
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
TMR2IF
TMR1IF
0000 0000
0000 0000
0111 1111
--00 0000
--00 0000
--11 1111
0000 0000
0000 0000
0111 1111
--00 0000
--00 0000
--11 1111
RC2IF
RC2IE
RC2IP
TX2IF TMR4IF CCP5IF
TX2IE TMR4IE CCP5IE
TX2IP TMR4IP CCP5IP
CCP4IF
CCP4IE
CCP4IP
CCP3IF
CCP3IE
CCP3IP
—
—
(1)
RCSTAx
TXREGx
SPEN
RX9
SREN
CREN ADDEN
FERR
OERR
RX9D
0000 000x
0000 0000
0000 -010
0000 0000
0000 000x
0000 0000
0000 -010
0000 0000
(1)
USART Transmit Register
CSRC TX9 TXEN
Baud Rate Generator Register
(1)
TXSTAx
SYNC
—
BRGH
TRMT
TX9D
(1)
SPBRGx
Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.
Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’ indicates
the particular module. Bit names and RESET values are identical between modules.
DS39609A-page 208
Advance Information
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
