PIC18FXX20
To set up a Synchronous Slave Reception:
18.4.2
USART SYNCHRONOUS SLAVE
RECEPTION
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. If interrupts are desired, set enable bit RCxIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
5. Flag bit RCxIF will be set when reception is com-
plete. An interrupt will be generated if enable bit
RCxIE was set.
6. Read the RCSTAx register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode and bit SREN, which is a “don't care” in Slave
mode.
If receive is enabled by setting bit CREN prior to the
SLEEPinstruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register,
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector.
7. Read the 8-bit received data by reading the
RCREGx register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 18-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000
0000 0000
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
PSPIF
PSPIE
PSPIP
—
—
—
ADIF
ADIE
ADIP
—
—
—
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
CREN
SSPIF
SSPIE
SSPIP
CCP1IF TMR2IF TMR1IF 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000
CCP1IP TMR2IP TMR1IP 0111 1111
0000 0000
0000 0000
0111 1111
--00 0000
--00 0000
--11 1111
0000 000x
0000 0000
0000 -010
0000 0000
TMR4IF CCP5IF CCP4IF CCP3IF --00 0000
TMR4IE CCP5IE CCP4IE CCP3IE --00 0000
TMR4IP CCP5IP CCP4IP CCP3IP --11 1111
(1)
RCSTAx
TXREGx
SPEN
RX9
ADDEN
FERR
OERR
RX9D
0000 000x
0000 0000
0000 -010
0000 0000
(1)
USART Receive Register
CSRC TX9 TXEN
Baud Rate Generator Register
(1)
TXSTAx
SPBRGx
SYNC
—
BRGH
TRMT
TX9D
(1)
Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Reception.
Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’
indicates the particular module. Bit names and RESET values are identical between modules.
DS39609A-page 212
Advance Information
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
