PIC18FXX20
18.2.2
USART ASYNCHRONOUS
RECEIVER
18.2.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
The USART receiver block diagram is shown in
Figure 18-4. The data is received on the pin
(RC7/RX1/DT1 or RG2/RX2/DT2) and drives the data
recovery block. The data recovery block is actually a
high speed shifter operating at 16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at FOSC. This mode would typically be used
in RS-232 systems.
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGx register for the appropri-
ate baud rate. If a high speed baud rate is
required, set the BRGH bit.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
To set up an Asynchronous Reception:
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
7. The RCxIF bit will be set when reception is com-
plete. The interrupt will be Acknowledged if the
RCxIE and GIE bits are set.
8. Read the RCSTAx register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 18.1).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit RCxIE.
4. If 9-bit reception is desired, set bit RX9.
5. Enable the reception by setting bit CREN.
6. Flag bit RCxIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCxIE was set.
7. Read the RCSTAx register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read RCREGx to determine if the device is
being addressed.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 18-4:
USART RECEIVE BLOCK DIAGRAM
FERR
OERR
CREN
x64 Baud Rate CLK
÷ 64
or
RSR Register
LSb
MSb
SPBRG
÷ 16
0
1
7
STOP (8)
START
• • •
Baud Rate Generator
RX9
RX pin
Pin Buffer
and Control
Data
Recovery
RX9D
RCREG Register
FIFO
SPEN
8
Interrupt
RCIF
RCIE
Data Bus
DS39609A-page 206
Advance Information
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
