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PIC18F8620-I/PT 参数 Datasheet PDF下载

PIC18F8620-I/PT图片预览
型号: PIC18F8620-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器和处理器外围集成电路PC时钟
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18FXX20  
17.4.12 ACKNOWLEDGE SEQUENCE  
17.4.13 STOP CONDITION TIMING  
TIMING  
A STOP bit is asserted on the SDA pin at the end of a  
receive/transmit by setting the STOP sequence enable  
bit, PEN (SSPCON2<2>). At the end of  
An Acknowledge sequence is enabled by setting the  
a
Acknowledge  
sequence  
enable  
bit,  
ACKEN  
receive/transmit, the SCL line is held low after the fall-  
ing edge of the ninth clock. When the PEN bit is set, the  
master will assert the SDA line low. When the SDA line  
is sampled low, the baud rate generator is reloaded and  
counts down to ‘0’. When the baud rate generator times  
out, the SCL pin will be brought high, and one TBRG  
(baud rate generator rollover count) later, the SDA pin  
will be de-asserted. When the SDA pin is sampled high  
while SCL is high, the P bit (SSPSTAT<4>) is set. A  
TBRG later, the PEN bit is cleared and the SSPIF bit is  
set (Figure 17-24).  
(SSPCON2<4>). When this bit is set, the SCL pin is  
pulled low and the contents of the Acknowledge data bit  
are presented on the SDA pin. If the user wishes to gen-  
erate an Acknowledge, then the ACKDT bit should be  
cleared. If not, the user should set the ACKDT bit before  
starting an Acknowledge sequence. The baud rate gen-  
erator then counts for one rollover period (TBRG) and the  
SCL pin is de-asserted (pulled high). When the SCL pin  
is sampled high (clock arbitration), the baud rate gener-  
ator counts for TBRG. The SCL pin is then pulled low. Fol-  
lowing this, the ACKEN bit is automatically cleared, the  
baud rate generator is turned off and the MSSP module  
then goes into IDLE mode (Figure 17-23).  
17.4.13.1 WCOL Status Flag  
If the user writes the SSPBUF when a STOP sequence  
is in progress, then the WCOL bit is set and the con-  
tents of the buffer are unchanged (the write doesn’t  
occur).  
17.4.12.1 WCOL Status Flag  
If the user writes the SSPBUF when an Acknowledge  
sequence is in progress, then WCOL is set and the con-  
tents of the buffer are unchanged (the write doesn’t occur).  
FIGURE 17-23:  
ACKNOWLEDGE SEQUENCE WAVEFORM  
Acknowledge sequence starts here,  
Write to SSPCON2  
ACKEN automatically cleared  
ACKEN = 1, ACKDT = 0  
TBRG  
ACK  
TBRG  
SDA  
SCL  
D0  
8
9
SSPIF  
Cleared in  
Set SSPIF at the end  
of receive  
Cleared in  
software  
software  
Set SSPIF at the end  
of Acknowledge sequence  
Note: TBRG = one baud rate generator period.  
FIGURE 17-24:  
STOP CONDITION RECEIVE OR TRANSMIT MODE  
SCL = 1for TBRG, followed by SDA = 1for TBRG  
Write to SSPCON2  
Set PEN  
after SDA sampled high. P bit (SSPSTAT<4>) is set.  
PEN bit (SSPCON2<2>) is cleared by  
hardware and the SSPIF bit is set  
Falling edge of  
9th clock  
TBRG  
SCL  
SDA  
ACK  
P
TBRG  
TBRG  
TBRG  
SCL brought high after TBRG  
SDA asserted low before rising edge of clock  
to setup STOP condition  
Note: TBRG = one baud rate generator period.  
DS39609A-page 190  
Advance Information  
2003 Microchip Technology Inc.  
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