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PIC18F8620-I/PT 参数 Datasheet PDF下载

PIC18F8620-I/PT图片预览
型号: PIC18F8620-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器和处理器外围集成电路PC时钟
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18FXX20  
17.4.10.3 ACKSTAT Status Flag  
In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is  
cleared when the slave has sent an Acknowledge  
(ACK = 0), and is set when the slave does not Acknowl-  
edge (ACK = 1). A slave sends an Acknowledge when  
it has recognized its address (including a general call),  
or when the slave has properly received its data.  
17.4.10 I2C MASTER MODE  
TRANSMISSION  
Transmission of a data byte, a 7-bit address, or the  
other half of a 10-bit address is accomplished by simply  
writing a value to the SSPBUF register. This action will  
set the buffer full flag bit, BF, and allow the baud rate  
generator to begin counting and start the next transmis-  
sion. Each bit of address/data will be shifted out onto  
the SDA pin after the falling edge of SCL is asserted  
(see data hold time specification parameter #106). SCL  
is held low for one baud rate generator rollover count  
(TBRG). Data should be valid before SCL is released  
high (see data setup time specification parameter  
#107). When the SCL pin is released high, it is held that  
way for TBRG. The data on the SDA pin must remain  
stable for that duration and some hold time, after the  
next falling edge of SCL. After the eighth bit is shifted  
out (the falling edge of the eighth clock), the BF flag is  
cleared and the master releases SDA. This allows the  
slave device being addressed to respond with an ACK  
bit during the ninth bit time if an address match  
occurred, or if data was received properly. The status  
of ACK is written into the ACKDT bit on the falling edge  
of the ninth clock. If the master receives an Acknowl-  
edge, the Acknowledge status bit, ACKSTAT, is  
cleared. If not, the bit is set. After the ninth clock, the  
SSPIF bit is set and the master clock (baud rate gener-  
ator) is suspended until the next data byte is loaded into  
the SSPBUF, leaving SCL low and SDA unchanged  
(Figure 17-21).  
After the write to the SSPBUF, each bit of address will  
be shifted out on the falling edge of SCL, until all seven  
address bits and the R/W bit are completed. On the fall-  
ing edge of the eighth clock, the master will de-assert  
the SDA pin, allowing the slave to respond with an  
Acknowledge. On the falling edge of the ninth clock, the  
master will sample the SDA pin to see if the address  
was recognized by a slave. The status of the ACK bit is  
loaded into the ACKSTAT status bit (SSPCON2<6>).  
Following the falling edge of the ninth clock transmis-  
sion of the address, the SSPIF is set, the BF flag is  
cleared and the baud rate generator is turned off until  
another write to the SSPBUF takes place, holding SCL  
low and allowing SDA to float.  
17.4.11 I2C MASTER MODE RECEPTION  
Master mode reception is enabled by programming the  
receive enable bit, RCEN (SSPCON2<3>).  
Note: The MSSP module must be in an IDLE  
state before the RCEN bit is set, or the  
RCEN bit will be disregarded.  
The baud rate generator begins counting, and on each  
rollover, the state of the SCL pin changes (high to  
low/low to high) and data is shifted into the SSPSR.  
After the falling edge of the eighth clock, the receive  
enable flag is automatically cleared, the contents of the  
SSPSR are loaded into the SSPBUF, the BF flag bit is  
set, the SSPIF flag bit is set and the baud rate genera-  
tor is suspended from counting, holding SCL low. The  
MSSP is now in IDLE state, awaiting the next com-  
mand. When the buffer is read by the CPU, the BF flag  
bit is automatically cleared. The user can then send an  
Acknowledge bit at the end of reception, by setting the  
Acknowledge sequence enable bit, ACKEN  
(SSPCON2<4>).  
17.4.11.1 BF Status Flag  
In receive operation, the BF bit is set when an address  
or data byte is loaded into SSPBUF from SSPSR. It is  
cleared when the SSPBUF register is read.  
17.4.11.2 SSPOV Status Flag  
In receive operation, the SSPOV bit is set when 8 bits  
are received into the SSPSR and the BF flag bit is  
already set from a previous reception.  
17.4.11.3 WCOL Status Flag  
If the user writes the SSPBUF when a receive is  
already in progress (i.e., SSPSR is still shifting in a data  
byte), the WCOL bit is set and the contents of the buffer  
are unchanged (the write doesn’t occur).  
17.4.10.1 BF Status Flag  
In Transmit mode, the BF bit (SSPSTAT<0>) is set  
when the CPU writes to SSPBUF and is cleared when  
all 8 bits are shifted out.  
17.4.10.2 WCOL Status Flag  
If the user writes the SSPBUF when a transmit is  
already in progress (i.e., SSPSR is still shifting out a  
data byte), the WCOL is set and the contents of the  
buffer are unchanged (the write doesn’t occur).  
WCOL must be cleared in software.  
2003 Microchip Technology Inc.  
Advance Information  
DS39609A-page 187  
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