欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F8620-I/PT 参数 Datasheet PDF下载

PIC18F8620-I/PT图片预览
型号: PIC18F8620-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器和处理器外围集成电路PC时钟
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F8620-I/PT的Datasheet PDF文件第156页浏览型号PIC18F8620-I/PT的Datasheet PDF文件第157页浏览型号PIC18F8620-I/PT的Datasheet PDF文件第158页浏览型号PIC18F8620-I/PT的Datasheet PDF文件第159页浏览型号PIC18F8620-I/PT的Datasheet PDF文件第161页浏览型号PIC18F8620-I/PT的Datasheet PDF文件第162页浏览型号PIC18F8620-I/PT的Datasheet PDF文件第163页浏览型号PIC18F8620-I/PT的Datasheet PDF文件第164页  
PIC18FXX20  
SSPSR is the shift register used for shifting data in or  
out. SSPBUF is the buffer register to which data bytes  
are written to or read from.  
In receive operations, SSPSR and SSPBUF together  
create a double-buffered receiver. When SSPSR  
receives a complete byte, it is transferred to SSPBUF  
and the SSPIF interrupt is set.  
17.3.1  
REGISTERS  
The MSSP module has four registers for SPI mode  
operation. These are:  
• MSSP Control Register1 (SSPCON1)  
• MSSP Status Register (SSPSTAT)  
• Serial Receive/Transmit Buffer (SSPBUF)  
• MSSP Shift Register (SSPSR) - Not directly  
During transmission, the SSPBUF is not double-  
buffered. A write to SSPBUF will write to both SSPBUF  
and SSPSR.  
accessible  
SSPCON1 and SSPSTAT are the control and status  
registers in SPI mode operation. The SSPCON1 regis-  
ter is readable and writable. The lower 6 bits of the  
SSPSTAT are read only. The upper two bits of the  
SSPSTAT are read/write.  
REGISTER 17-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)  
R/W-0  
SMP  
R/W-0  
CKE  
R-0  
D/A  
R-0  
P
R-0  
S
R-0  
R/W  
R-0  
UA  
R-0  
BF  
bit 7  
bit 0  
bit 7  
bit 6  
SMP: Sample bit  
SPI Master mode:  
1= Input data sampled at end of data output time  
0= Input data sampled at middle of data output time  
SPI Slave mode:  
SMP must be cleared when SPI is used in Slave mode  
CKE: SPI Clock Edge Select bit  
When CKP = 0:  
1= Data transmitted on rising edge of SCK  
0= Data transmitted on falling edge of SCK  
When CKP = 1:  
1= Data transmitted on falling edge of SCK  
0= Data transmitted on rising edge of SCK  
bit 5  
bit 4  
D/A: Data/Address bit  
Used in I2C mode only  
P: STOP bit  
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is  
cleared.  
bit 3  
bit 2  
bit 1  
bit 0  
S: START bit  
Used in I2C mode only  
R/W: Read/Write bit information  
Used in I2C mode only  
UA: Update Address bit  
Used in I2C mode only  
BF: Buffer Full Status bit (Receive mode only)  
1= Receive complete, SSPBUF is full  
0= Receive not complete, SSPBUF is empty  
Legend:  
R = Readable bit  
- n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
DS39609A-page 158  
Advance Information  
2003 Microchip Technology Inc.  
 复制成功!