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PIC18F8620-I/PT 参数 Datasheet PDF下载

PIC18F8620-I/PT图片预览
型号: PIC18F8620-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器和处理器外围集成电路PC时钟
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18FXX20  
17.3 SPI Mode  
17.0 MASTER SYNCHRONOUS  
SERIAL PORT (MSSP)  
MODULE  
The SPI mode allows 8 bits of data to be synchronously  
transmitted and received simultaneously. All four  
modes of SPI are supported. To accomplish communi-  
cation, typically three pins are used:  
• Serial Data Out (SDO) - RC5/SDO  
• Serial Data In (SDI) - RC4/SDI/SDA  
• Serial Clock (SCK) - RC3/SCK/SCL/LVDIN  
Additionally, a fourth pin may be used when in a Slave  
mode of operation:  
• Slave Select (SS) - RF7/SS  
17.1 Master SSP (MSSP) Module  
Overview  
The Master Synchronous Serial Port (MSSP) module is  
a serial interface, useful for communicating with other  
peripheral or microcontroller devices. These peripheral  
devices may be serial EEPROMs, shift registers, dis-  
play drivers, A/D converters, etc. The MSSP module  
can operate in one of two modes:  
• Serial Peripheral Interface (SPI)  
• Inter-Integrated Circuit (I2C)  
- Full Master mode  
- Slave mode (with general address call)  
The I2C interface supports the following modes in  
hardware:  
Figure 17-1 shows the block diagram of the MSSP  
module when operating in SPI mode.  
FIGURE 17-1:  
MSSP BLOCK DIAGRAM  
(SPI MODE)  
Internal  
Data Bus  
• Master mode  
• Multi-Master mode  
• Slave mode  
Read  
Write  
SSPBUF reg  
SSPSR reg  
17.2 Control Registers  
RC4/SDI/SDA  
RC5/SDO  
The MSSP module has three associated registers.  
These include a status register (SSPSTAT) and two  
control registers (SSPCON1 and SSPCON2). The use  
of these registers and their individual configuration bits  
differ significantly, depending on whether the MSSP  
module is operated in SPI or I2C mode.  
Shift  
bit0  
Clock  
Additional details are provided under the individual  
sections.  
RF7/SS  
Control  
Enable  
SS  
Edge  
Select  
2
Clock Select  
SSPM3:SSPM0  
SMP:CKE  
4
TMR2 Output  
RC3/SCK/  
SCL  
(
)
2
2
Edge  
Select  
TOSC  
Prescaler  
4, 16, 64  
Data to TX/RX in SSPSR  
TRIS bit  
2003 Microchip Technology Inc.  
Advance Information  
DS39609A-page 157  
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