PIC18F6525/6621/8525/8621
8.2
Operation
8.0
8.1
8 x 8 HARDWARE MULTIPLIER
Introduction
Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
An 8 x 8 hardware multiplier is included in the ALU of the
PIC18F6525/6621/8525/8621 devices. By making the
multiply a hardware operation, it completes in a single
instruction cycle. This is an unsigned multiply that gives
a 16-bit result. The result is stored in the 16-bit product
register pair (PRODH:PRODL). The multiplier does not
affect any flags in the ALUSTA register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the signed bits of the
arguments, each argument’s Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
EXAMPLE 8-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
MOVF
MULWF ARG2
ARG1, W
;
• Higher computational throughput
; ARG1 * ARG2 ->
;
• Reduces code size requirements for multiply
algorithms
PRODH:PRODL
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
EXAMPLE 8-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
MOVF
ARG1, W
;
Table 8-1 shows a performance comparison between
Enhanced devices using the single-cycle hardware
multiply and performing the same function without the
hardware multiply.
MULWF ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
BTFSC ARG2, SB
SUBWF PRODH, F
;
;
- ARG1
MOVF
ARG2, W
BTFSC ARG1, SB
SUBWF PRODH, F
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
TABLE 8-1:
Routine
PERFORMANCE COMPARISON
Program
Time
@ 40 MHz @ 10 MHz @ 4 MHz
Cycles
(Max)
Multiply Method
Memory
(Words)
Without hardware multiply
Hardware multiply
13
1
69
1
6.9 µs
100 ns
9.1 µs
600 ns
24.2 µs
2.4 µs
25.4 µs
3.6 µs
27.6 µs
400 ns
36.4 µs
2.4 µs
69 µs
1 µs
8 x 8 unsigned
8 x 8 signed
Without hardware multiply
Hardware multiply
33
6
91
6
91 µs
6 µs
Without hardware multiply
Hardware multiply
21
24
52
36
242
24
254
36
96.8 µs
9.6 µs
102.6 µs
14.4 µs
242 µs
24 µs
254 µs
36 µs
16 x 16 unsigned
16 x 16 signed
Without hardware multiply
Hardware multiply
2005 Microchip Technology Inc.
DS39612B-page 85
MICROCHIP [ MICROCHIP ]
