PIC18F6525/6621/8525/8621
FIGURE 1-1:
PIC18F6525/6621 BLOCK DIAGRAM
Data Bus<8>
PORTA
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
Table Pointer<21>
inc/dec logic
Data Latch
21
8
8
Data RAM
(3.8 Kbytes)
21
RA5/AN4/LVDIN
OSC2/CLKO/RA6
Address Latch
12
20
PCLATU PCLATH
PORTB
RB0/INT0/FLT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
Address<12>
PCU PCH PCL
Program Counter
4
BSR
12
FSR0
4
Bank 0, F
Address Latch
FSR1
FSR2
Program Memory
(48/64 Kbytes)
31 Level Stack
12
Data Latch
inc/dec
logic
PORTC
Decode
RC0/T1OSO/T13CKI
RC1/T1OSI/ECCP2(1)/P2A(1)
RC2/ECCP1/P1A
Table Latch
8
16
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX1/CK1
RC7/RX1/DT1
ROM Latch
IR
PORTD
PORTE
8
RD7/PSP7 :RD0/PSP0
PRODH PRODL
8 x 8 Multiply
Instruction
Decode and
Control
RE0/RD/P2D
RE1/WR/P2C
RE2/CS/P2B
RE3/P3C
8
3
W
8
BITOP
8
8
Power-up
Timer
OSC2/CLKO
OSC1/CLKI
RE4/P3B
RE5/P1C
Timing
Generation
Oscillator
Start-up Timer
8
RE6/P1B
RE7/ECCP2(1)/P2A(1)
ALU<8>
Power-on
Reset
PORTF
RF0/AN5
8
Watchdog
Timer
RF1/AN6/C2OUT
RF2/AN7/C1OUT
RF3/AN8
Precision
Band Gap
Reference
Brown-out
Reset
RF4/AN9
RF5/AN10/CVREF
RF6/AN11
Test Mode
Select
RF7/SS
MCLR(2)
Timer2
VDD,VSS
Timer1
PORTG
RG0/ECCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
RG4/CCP5/P1D
MCLR/VPP/RG5(2)
Data
EEPROM
BOR
LVD
10-bit
ADC
Timer0
Timer3
Timer4
MSSP
Comparator ECCP1 ECCP2 ECCP3 CCP4 CCP5
EUSART1 EUSART2
Note 1: ECCP2/P2A are multiplexed with RC1 when CCP2MX is set, or RE7 when CCP2MX is not set.
2: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2005 Microchip Technology Inc.
DS39612B-page 9
MICROCHIP [ MICROCHIP ]
