PIC18F6585/8585/6680/8680
FIGURE 10-2:
BLOCK DIAGRAM OF
RA3:RA0AND RA5PINS
FIGURE 10-3:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
RD LATA
RD LATA
Data
Bus
Data
Bus
D
Q
D
Q
Q
WR LATA
or
PORTA
WR LATA
or
PORTA
VDD
I/O pin(1)
Q
Data Latch
CK
CK
P
N
Data Latch
I/O pin(1)
D
Q
N
D
Q
VSS
WR TRISA
RD TRISA
Schmitt
Trigger
Input
WR TRISA
RD TRISA
CK
Q
VSS
Analog
Q
CK
TRIS Latch
TRIS Latch
Input
Buffer
Mode
TTL
Input
Buffer
Q
D
Q
D
EN
EN
EN
RD PORTA
RD PORTA
TMR0 Clock Input
To A/D Converter and LVD Modules
Note 1: I/O pins have protection diodes to VDD and VSS.
Note 1: I/O pins have protection diodes to VDD and VSS.
FIGURE 10-4:
BLOCK DIAGRAM OF RA6 PIN (WHEN ENABLED AS I/O)
ECRA6 or RCRA6 Enable
Data Bus
RD LATA
D
Q
Q
VDD
P
WR LATA or PORTA
CK
Data Latch
I/O pin(1)
N
D
Q
WR TRISA
VSS
CK
Q
TRIS Latch
TTL
Input
Buffer
TRISA
RD
ECRA6 or RCRA6 Enable
Q
D
EN
RD PORTA
Note 1: I/O pins have protection diodes to VDD and VSS.
DS30491C-page 126
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
