PIC18F6585/8585/6680/8680
10.0
I/O PORTS
10.1
Depending on the device selected, there are either seven
or nine I/O ports available on PIC18F6X8X/8X8X
devices. Some of their pins are multiplexed with one or
more alternate functions from the other peripheral fea-
tures on the device. In general, when a peripheral is
enabled, that pin may not be used as a general purpose
I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (output latch)
The Data Latch register (LAT) is useful for read-modify-
write operations on the value that the I/O pins are
driving.
A simplified version of a generic I/O port and its
operation is shown in Figure 10-1.
PORTA, TRISA and LATA
Registers
PORTA is a 7-bit wide, bidirectional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (=
1)
will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (=
0)
will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
The Data Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register read and write the latched output value for
PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The
RA4/T0CKI pin is a Schmitt Trigger input and an open-
drain output. All other RA port pins have TTL input
levels and full CMOS output drivers.
The RA6 pin is only enabled as a general I/O pin in
ECIO and RCIO Oscillator modes.
The other PORTA pins are multiplexed with analog
inputs and the analog V
REF
+ and V
REF
- inputs. The
operation of each pin is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register 1).
Note:
On a Power-on Reset, RA5 and RA3:RA0
are configured as analog inputs and read
as ‘0’. RA6 and RA4 are configured as
digital inputs.
FIGURE 10-1:
SIMPLIFIED BLOCK
DIAGRAM OF
PORT/LAT/TRIS
OPERATION
RD LAT
TRIS
D
WR LAT +
WR Port
Q
CK
Data Latch
Data Bus
RD Port
I/O pin
The TRISA register controls the direction of the RA pins
even when they are being used as analog inputs. The
user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 10-1:
CLRF
PORTA
;
;
;
;
;
;
;
;
;
;
;
;
;
INITIALIZING PORTA
Initialize PORTA by
clearing output
data latches
Alternate method
to clear output
data latches
Configure A/D
for digital inputs
Value used to
initialize data
direction
Set RA<3:0> as inputs
RA<5:4> as outputs
CLRF
LATA
MOVLW
MOVWF
MOVLW
0Fh
ADCON1
0CFh
MOVWF
TRISA
2004 Microchip Technology Inc.
DS30491C-page 125
MICROCHIP [ MICROCHIP TECHNOLOGY ]
