PIC18F6585/8585/6680/8680
FIGURE 1-1:
PIC18F6X8X BLOCK DIAGRAM
Data Bus<8>
PORTA
RA0/AN0
RA1/AN1
Table Pointer<21>
Data Latch
21
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
8
8
Data RAM
(3328 bytes)
inc/dec logic
21
RA5/AN4/LVDIN
OSC2/CLKO/RA6
Address Latch
12
21
PCLATH
PCLATU
PORTB
RB2/INT2:RB0/INT0
RB3/INT3
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
Address<12>
PCU PCH PCL
Program Counter
4
BSR
12
FSR0
4
Bank0, F
Address Latch
FSR1
FSR2
Program Memory
(48 Kbytes)
31 Level Stack
12
Data Latch
PORTC
inc/dec
logic
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Decode
Table Latch
8
16
ROM Latch
IR
PORTD
PORTE
8
RD7/PSP7:RD0/PSP0
PRODH PRODL
8 x 8 Multiply
Instruction
Decode &
Control
RE0/RD
RE1/WR
RE2/CS
RE3
8
3
W
8
BITOP
8
8
Power-up
Timer
RE4
OSC2/CLKO/RA6
OSC1/CLKI
RE5/P1C
RE6/P1B
RE7/CCP2(1)
Timing
Generation
Oscillator
Start-up Timer
8
ALU<8>
Power-on
Reset
PORTF
RF0/AN5
8
RF1/AN6/C2OUT
RF2/AN7/C1OUT
RF3/AN8/C2IN+
RF4/AN9/C2IN-
RF5/AN10/C1IN+/CVREF
RF6/AN11/C1IN-
RF7/SS
Watchdog
Timer
Precision
Band Gap
Reference
Brown-out
Reset
Test Mode
Select
RG5/
VDD, VSS
MCLR
PORTG
RG0/CANTX1
RG1/CANTX2
RG2/CANRX
RG3
RG4/P1D
RG5/MCLR/VPP
BOR
LVD
Timer3
Timer0
Timer1
Timer2
Synchronous
Serial Port
10-bit
ADC
CCP2
ECCP1
Comparator
AUSART
ECAN Module
Data EEPROM
Note 1: The CCP2 pin placement depends on the CCP2MX and Processor mode settings.
DS30491C-page 10
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
