PIC18F2331/2431/4331/4431
Timer2...............................................................................136
Associated Registers ................................................137
Interrupt.....................................................................137
Operation ..................................................................136
Postscaler. See Postscaler, Timer2.
Low-Voltage Detect .................................................. 260
Low-Voltage Detect Characteristics.......................... 342
Noise Filter................................................................ 170
Pulse-Width Measurement Mode ............................. 157
PWM Output............................................................. 149
PWM Output Override (Example 1).......................... 197
PWM Output Override (Example 2).......................... 197
PWM Override Bits in Complementary Mode........... 195
PWM Period Buffer Updates in
Continuous Up/Down Count Mode................... 186
PWM Period Buffer Updates in
Free-Running Mode.......................................... 186
PWM Time Base Interrupt, Continuous
Prescaler. See Prescaler, Timer2.
PR2 Register.............................................................136
SSP Clock Shift................................................. 136, 137
TMR2 Register..........................................................136
TMR2 to PR2 Match Interrupt ........................... 136, 149
Timer5...............................................................................139
Associated Registers ................................................143
Interrupt.....................................................................142
Noise Filter................................................................142
Operation ..................................................................140
Continuous Count and Single-Shot...................141
Sleep Mode.......................................................142
Prescaler...................................................................141
Special Event Trigger
Up/Down Count Mode ...................................... 183
PWM Time Base Interrupt, Continuous
Up/Down Count Mode with
Double Updates................................................ 184
PWM Time Base Interrupt, Free-Running Mode ...... 181
PWM Time Base Interrupt, Single-Shot Mode.......... 182
QEI Inputs When Sampled by Filter ......................... 165
QEI Reset on Period Match...................................... 165
QEI Reset with the Index Input................................. 166
Reset, Watchdog Timer (WDT), Oscillator
Output ...............................................................142
Reset Input........................................................142
16-Bit Read/Write and Write Modes .........................141
16-Bit Read-Modify-Write..........................................141
Timing Diagrams
Start-up Timer (OST), Power-up
Automatic Baud Rate Calculation .............................225
Auto-Wake-up Bit (WUE) During
Timer (PWRT) .................................................. 349
Send Break Character Sequence............................. 232
Slow Rise Time (MCLR Tied to VDD,
Normal Operation..............................................231
Auto-Wake-up Bit (WUE) During Sleep ....................231
Brown-out Reset (BOR)............................................349
Capture/Compare/PWM (All CCP Modules).............352
CAPx Interrupts and IC1 Special Event Trigger........159
CLKO and I/O ...........................................................348
Clock, Instruction Cycle ..............................................65
Dead-Time Insertion for Complementary PWM ........191
Duty Cycle Update Times in Continuous
VDD Rise > TPWRT)............................................. 52
SPI Mode (Master Mode).......................................... 210
SPI Mode (Slave Mode with CKE = 0)...................... 210
SPI Mode (Slave Mode with CKE = 1)...................... 211
Start of Center-Aligned PWM ................................... 189
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD) ........................................... 53
Time-out Sequence on Power-up
Up/Down Count Mode.......................................188
Duty Cycle Update Times in Continuous
(MCLR Not Tied to VDD): Case 1 ....................... 51
Time-out Sequence on Power-up
Up/Down Count Mode with
(MCLR Not Tied to VDD): Case 2 ....................... 52
Time-out Sequence on Power-up
Double Updates ................................................189
Edge Capture Mode..................................................156
Edge-Aligned PWM...................................................188
EUSART Asynchronous Reception ..........................230
EUSART Asynchronous Transmission .....................227
EUSART Asynchronous Transmission
(Back to Back)...................................................227
EUSART Synchronous Receive (Master/Slave) .......360
EUSART Synchronous Reception
(Master Mode, SREN).......................................235
EUSART Synchronous Transmission .......................233
EUSART Synchronous Transmission
(Through TXEN)................................................234
EUSART SynchronousTransmission
(Master/Slave)...................................................360
Example SPI Master Mode (CKE = 0) ......................353
Example SPI Master Mode (CKE = 1) ......................354
Example SPI Slave Mode (CKE = 0) ........................355
Example SPI Slave Mode (CKE = 1) ........................356
External Clock (All Modes Except PLL) ....................346
Fail-Safe Clock Monitor.............................................278
Input Capture on State Change, Hall Effect
(MCLR Tied to VDD, VDD Rise TPWRT)............... 51
Timer0 and Timer1 External Clock ........................... 351
Transition for Entry to Idle Mode................................. 44
Transition for Entry to SEC_RUN Mode ..................... 41
Transition for Entry to Sleep Mode ............................. 43
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ......................................... 276
Transition for Wake From Idle to Run Mode............... 44
Transition for Wake From Sleep (HSPLL) .................. 43
Transition From RC_RUN Mode to
PRI_RUN Mode.................................................. 42
Transition From SEC_RUN Mode to
PRI_RUN Mode (HSPLL)................................... 41
Transition to RC_RUN Mode...................................... 42
Velocity Measurement .............................................. 168
Timing Diagrams and Specifications ................................ 346
Capture/Compare/PWM Requirements
(All CCP Modules)............................................ 352
CLKO and I/O Requirements.................................... 348
EUSART Synchronous Receive Requirements........ 360
EUSART Synchronous Transmission
Sensor Mode....................................................158
I C Bus Data.............................................................357
I C Bus Start/Stop Bits..............................................357
I C Reception (7-Bit Address)...................................214
Requirements ................................................... 360
Example SPI Mode Requirements
(Master Mode, CKE = 0)................................... 353
Example SPI Mode Requirements
2
2
2
2
I C Transmission (7-Bit Address) .............................215
(Master Mode, CKE = 1)................................... 354
DS39616D-page 386
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