PIC18F2331/2431/4331/4431
TABLE 21-3: SUMMARY OF A/D REGISTERS
Reset Values
on Page:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
PIE1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
SSPIF
SSPIE
SSPIP
—
TMR0IF
CCP1IF
CCP1IE
CCP1IP
LVDIF
INT0IF
TMR2IF
TMR2IE
TMR2IP
—
RBIF
54
57
57
57
57
57
57
56
56
56
56
56
56
56
56
56
57
57
57
57
57
—
—
ADIF
ADIE
ADIP
—
RCIF
RCIE
RCIP
—
TXIF
TXIE
TXIP
EEIF
EEIE
EEIP
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
IPR1
PIR2
PIE2
—
OSCFIF
OSCFIE
OSCFIP
—
—
—
LVDIE
—
IPR2
—
—
—
LVDIP
—
ADRESH A/D Result Register High Byte
ADRESL
ADCON0
ADCON1
ADCON2
ADCON3
ADCHS
ANSEL0
ANSEL1
PORTA
A/D Result Register Low Byte
—
—
ACONV ACSCH ACMOD1 ACMOD0 GO/DONE
ADON
ADPNT0
ADCS0
SSRC0
GASEL0
ANS0
VCFG1
ADFM
ADRS1
VCFG0
ACQT3
ADRS0
—
FIFOEN BFEMT BFOVFL
ADPNT1
ADCS1
SSRC1
GASEL1
ANS1
—
ACQT2 ACQT1
SSRC4
ACQT0
SSRC3
ADCS2
SSRC2
—
GDSEL1 GDSEL0 GBSEL1 GBSEL0 GCSEL1 GCSEL0
ANS7(6)
ANS6(6) ANS5(6)
ANS4
—
ANS3
—
ANS2
—
—
—
—
ANS8(5)
RA7(4)
RA6(4)
RA5
RA4
RA3
RA2
RA1
RA0
TRISA
TRISA7(4) TRISA6(4) PORTA Data Direction Register
PORTE(2)
TRISE(3)
LATE(3)
—
—
—
—
—
—
—
—
—
—
—
—
RE3(1,3)
RA2(3)
RA1(3)
RA0(3)
—
PORTE Data Direction Register
LATE Data Output Register
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: The RE3 port bit is available only as an input pin when the MCLRE bit in the CONFIG3H register is ‘0’.
2: This register is not implemented on PIC18F2331/2431 devices.
3: These bits are not implemented on PIC18F2331/2431 devices.
4: These pins may be configured as port pins depending on the oscillator mode selected.
5: ANS5 through ANS8 are available only on the PIC18F4331/4431 devices.
6: Not available on 28-pin devices.
2010 Microchip Technology Inc.
DS39616D-page 255
MICROCHIP [ MICROCHIP ]
