PIC18F2331/2431/4331/4431
FIGURE 20-2:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TXREG Register
TXIF
TXIE
8
MSb
(8)
LSb
0
Pin Buffer
and Control
TSR Register
RC6/TX/CK/SS Pin
Interrupt
Baud Rate CLK
SPBRG
TXEN
TRMT
SPEN
BRG16
SPBRGH
TX9
Baud Rate Generator
TX9D
FIGURE 20-3:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK/SS
(pin)
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TXIF bit
(Interrupt Reg. Flag)
1 TCY
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 20-4:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Start bit
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK/SS
(pin)
Start bit
Word 2
bit 0
bit 1
Word 1
bit 7/8
bit 0
Stop bit
1 TCY
TXIF bit
(Interrupt Reg. Flag)
1 TCY
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 2
Transmit Shift Reg.
Word 1
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
2010 Microchip Technology Inc.
DS39616D-page 227
MICROCHIP [ MICROCHIP ]
