PIC18F2331/2431/4331/4431
This allows the user to verify that no carry occurred for 8-
bit modes by checking for 00h in the SPBRGH register.
Refer to Table 20-4 for counter clock rates to the BRG.
20.2.3
AUTO-BAUD RATE DETECT
The Enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCIF interrupt is set
once the fifth rising edge on RX is detected. The value
in the RCREG needs to be read to clear the RCIF
interrupt. RCREG content should be discarded.
The automatic baud rate measurement sequence
(Figure 20-1) begins whenever a Start bit is received and
the ABDEN bit is set. The calculation is self-averaging.
Note 1: If the WUE bit is set with the ABDEN bit,
Auto-Baud Rate Detection will occur on
the byte following the Break character
(see Section 20.3.4 “Auto-Wake-up on
Sync Break Character”).
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG. In
ABD mode, the internal Baud Rate Generator is used
as a counter to time the bit period of the incoming serial
byte stream.
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible
due to bit error rates. Overall system timing
and communication baud rates must be
taken into consideration when using the
Auto-Baud Rate Detection feature.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto-Baud Detect
must receive a byte with the value of 55h (ASCII “U”,
which is also the LIN/J2602 bus Sync character) in
order to calculate the proper bit rate. The measurement
takes over both a low and a high bit time in order to
minimize any effects caused by asymmetry of the
incoming signal. After a Start bit, the SPBRG begins
counting up, using the preselected clock source on the
first rising edge of RX. After eight bits on the RX pin, or
the fifth rising edge, an accumulated value totalling the
proper BRG period is left in the SPBRGH:SPBRG
registers. Once the 5th edge is seen (should
correspond to the Stop bit), the ABDEN bit is
automatically cleared.
3: To maximize baud rate range, setting
the BRG16 bit is recommended if the
auto-baud feature is used.
TABLE 20-4: BRG COUNTER CLOCK
RATES
BRG16 BRGH
BRG Counter Clock
While calibrating the baud rate period, the BRG regis-
ters are clocked at 1/8th the preconfigured clock rate.
The BRG clock can be configured by the BRG16 and
BRGH bits. The BRG16 bit must be set to use both
SPBRG and SPBRGH as a 16-bit counter.
0
0
1
1
0
1
0
1
FOSC/512
FOSC/256
FOSC/128
FOSC/32
FIGURE 20-1:
AUTOMATIC BAUD RATE CALCULATION(1)
BRG Value
XXXXh
0000h
001Ch
Edge #2
Bit 3
Edge #3
Edge #4
Bit 7
Bit 6
Edge #5
Stop Bit
Edge #1
Bit 1
Bit 5
Start
Bit 0
Bit 2
Bit 4
RX Pin
BRG Clock
Auto-Cleared
Set by user
ABDEN bit
RCIF bit
(Interrupt)
Read
RCREG
XXXXh
XXXXh
1Ch
00h
SPBRG
SPBRGH
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
2010 Microchip Technology Inc.
DS39616D-page 225
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