PIC18F2331/2431/4331/4431
18.4.4
INTERRUPTS IN DOUBLE UPDATE
MODE
Note:
Do not change the PTMOD bits while
PTEN is active; it will yield unexpected
results. To change the PWM Timer mode
of operation, first clear the PTEN bit, load
the PTMOD bits with the required data
and then set PTEN.
This mode is available in Continuous Up/Down Count
mode. In the Double Update mode (PTMOD<1:0> = 11),
an interrupt event is generated each time the PTMR
register is equal to zero and each time the PTMR
matches with PTPER register. Figure 18-8 shows the
interrupts in Continuous Up/Down Count mode with
double updates.
The Double Update mode provides two additional
functions to the user in Center-Aligned mode.
1. The control loop bandwidth is doubled because
the PWM duty cycles can be updated twice per
period.
2. Asymmetrical center-aligned PWM waveforms
can be generated, which are useful for
minimizing output waveform distortion in certain
motor control applications.
FIGURE 18-8:
PWM TIME BASE INTERRUPT, CONTINUOUS UP/DOWN COUNT MODE WITH
DOUBLE UPDATES
A: PRESCALER = 1:1
Case 1: PTMR Counting Upwards
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
OSC1
2
PTMR
3FDh
3FEh
3FFh
3FEh
3FDh
PTDIR bit
PTMR_INT_REQ
PTIF bit
1
1
1
1
Case 2: PTMR Counting Downwards
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
OSC1
PTMR
PTDIR bit
002h
001h
000h
001h
002h
PTMR_INT_REQ
1
1
1
1
PTIF bit
Note 1: Interrupt flag bit, PTIF, is sampled here (every Q1).
2: PWM Time Base Period register, PTPER, is loaded with the value, 3FFh, for this example.
DS39616D-page 184
2010 Microchip Technology Inc.
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