PIC18F2331/2431/4331/4431
16.5.1
PWM PERIOD
16.5 PWM Mode
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following equation:
In Pulse-Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
EQUATION 16-1:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
PWM frequency is defined as 1/[PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:
Figure 16-3 shows a simplified block diagram of the
CCP1 module in PWM mode.
• TMR2 is cleared
For a step-by-step procedure on how to set up the
CCP1 module for PWM operation, see Section 16.5.3
“Setup for PWM Operation”.
• The CCP1 pin is set (if PWM duty cycle = 0%, the
CCP1 pin will not be set)
• The PWM duty cycle is copied from CCPR1L into
CCPR1H
FIGURE 16-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
Note: The Timer2 postscaler (see Section 14.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
CCP1CON<5:4>
Duty Cycle Registers
CCPR1L
16.5.2
PWM DUTY CYCLE
CCPR1H (Slave)
Comparator
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The PWM duty cycle is
calculated by the following equation:
R
S
Q
RC2/CCP1
(Note 1)
TMR2
TRISC<2>
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
EQUATION 16-2:
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 Prescale Value)
Note 1: 8-bit timer is concatenated with 2-bit internal
Q clock or 2 bits of the prescaler to create
10-bit time base.
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not copied into
CCPR1H until a match between PR2 and TMR2 occurs
(i.e., the period is complete). In PWM mode, CCPR1H
is a read-only register.
A PWM output (Figure 16-4) has a time base
(period) and a time that the output is high (duty
cycle). The frequency of the PWM is the inverse of
the period (1/period).
FIGURE 16-4:
PWM OUTPUT
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
2010 Microchip Technology Inc.
DS39616D-page 149
MICROCHIP [ MICROCHIP ]
