PIC18F2331/2431/4331/4431
Input Channel 1 (IC1) includes a Special Event
Trigger that can be configured for use in Velocity
17.1 Input Capture
The Input Capture (IC) submodule implements the
following features:
Measurement mode. Its block diagram is shown in
Figure 17-2. IC2 and IC3 are similar, but lack the
Special Event Trigger features or additional velocity
measurement logic. A representative block diagram is
shown in Figure 17-3. Please note that the time base
is Timer5.
• Three channels of independent input capture
(16-bits/channel) on the CAP1, CAP2 and CAP3
pins
• Edge-Trigger, Period or Pulse-Width
Measurement Operating modes for each channel
• Programmable prescaler on every input capture
channel
• Special Event Trigger output (IC1 only)
• Selectable noise filters on each capture input
FIGURE 17-2:
INPUT CAPTURE BLOCK DIAGRAM FOR IC1
CAP1 Pin
and
Mode
Select
Prescaler
1, 4, 16
Clock
Noise
Filter
CAP1BUF/VELR(1)
3
4
FLTCK<2:0>
Q Clocks
CAP1M<3:0>
IC1IF
Reset
IC1_TR
TMR5
Reset
Control
Special
Event Trigger
Reset
Clock/
Reset/
Interrupt
Decode
Logic
Timer5 Logic
1
CAP1BUF_clk
MUX
First Event
Reset
0
Timer5 Reset
Timer
velcap(2)
Reset
Control
VELM
Q Clocks
CAP1M<3:0>
Note 1: CAP1BUF register is reconfigured as VELR register when QEI mode is active.
2: QEI generated velocity pulses, vel_out, are downsampled to produce this velocity capture signal.
2010 Microchip Technology Inc.
DS39616D-page 153
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